{"id":807225,"url":"http://patchwork.ozlabs.org/api/1.0/patches/807225/?format=json","project":{"id":7,"url":"http://patchwork.ozlabs.org/api/1.0/projects/7/?format=json","name":"Linux network development","link_name":"netdev","list_id":"netdev.vger.kernel.org","list_email":"netdev@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<1504031985-52808-2-git-send-email-f.fainelli@gmail.com>","date":"2017-08-29T18:39:42","name":"[net-next,1/4] net: systemport: Use correct I/O accessors","commit_ref":null,"pull_url":null,"state":"superseded","archived":true,"hash":"85571debdb86d0c256fde64591065b7edd7ec89a","submitter":{"id":2800,"url":"http://patchwork.ozlabs.org/api/1.0/people/2800/?format=json","name":"Florian Fainelli","email":"f.fainelli@gmail.com"},"delegate":{"id":34,"url":"http://patchwork.ozlabs.org/api/1.0/users/34/?format=json","username":"davem","first_name":"David","last_name":"Miller","email":"davem@davemloft.net"},"mbox":"http://patchwork.ozlabs.org/project/netdev/patch/1504031985-52808-2-git-send-email-f.fainelli@gmail.com/mbox/","series":[{"id":435,"url":"http://patchwork.ozlabs.org/api/1.0/series/435/?format=json","date":"2017-08-29T18:39:41","name":"Endian fixes for SYSTEMPORT/SF2/MDIO","version":1,"mbox":"http://patchwork.ozlabs.org/series/435/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/807225/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"Ko7Bv2/P\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xhczC1VL6z9sPt\n\tfor ;\n\tWed, 30 Aug 2017 04:45:59 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751334AbdH2Sp4 (ORCPT );\n\tTue, 29 Aug 2017 14:45:56 -0400","from mail-wm0-f66.google.com ([74.125.82.66]:32791 \"EHLO\n\tmail-wm0-f66.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751215AbdH2Spz (ORCPT\n\t); Tue, 29 Aug 2017 14:45:55 -0400","by mail-wm0-f66.google.com with SMTP id e67so4644017wmd.0\n\tfor ; Tue, 29 Aug 2017 11:45:54 -0700 (PDT)","from stb-bld-04.irv.broadcom.com ([192.19.255.250])\n\tby smtp.gmail.com with ESMTPSA id\n\tc52sm7987181wrg.41.2017.08.29.11.45.50\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tTue, 29 Aug 2017 11:45:52 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=frGKJXgovrrI1aoA6wak8X8woz3TTGrDaLqeNPaYwwQ=;\n\tb=Ko7Bv2/PNkiZWsKCk4LHmVYQ0ap28GSf+bGVCHKEKmLIvaDw+eb7giWFeEZYDU1biG\n\tyl6/ObzEIuZmYtvJtFylgi7CzkDH9etCOZ49Ksgj0I/uQWsVKBVQHyDTv80IpjZ5QLWI\n\t7LyI6q/qwUV3eszp0k0k/7UnVnDBzm1tQvo0KHjjPMBuVsP9VMw+xSArkT8HzXf3AH6M\n\tEaxzIpkwyP3BavD6oB4651uvP5THqywbn09SRqGAD9COaBvLv2ExRQEHKygTs1mxCvrT\n\tCTesiUfzJsJg3yP71Tum3kleSULVVDd+iWtjMOPa/7YHZjWzkJG0q0iN4XDciwQDDwvC\n\tSTig==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=frGKJXgovrrI1aoA6wak8X8woz3TTGrDaLqeNPaYwwQ=;\n\tb=VE1CHFj2KY7g2QQZXNz9vFsdGSS8+FDoBZuMPylWxZADlFhahpVLEfZ4yg/WO9Y0qH\n\tNBw4pdos1nsWT0IPLJmCNkQ38h+tAsawwqsmPpo69YKwI9qVpC/jCjvAJpnxKTqLewWu\n\tXad22EzhhqoavVSie3W4Dz/rev0DZK39Lq/IK4QObzOQ4NKzKoBjdbmJdngBtrIzzzwB\n\tIMQw8nugKNXiz77LY2kWKjgS25I6mFsLbbwCwCMfpi4MnEuSWqyo3L9hAUCvPLSnWl+z\n\tWLiZsI8wEQM9BtgVBHbBJRRroUVvKTyS7PQIuAqA+QYMX4Tsdst/mU/6Mobokegf0ngS\n\tMsQA==","X-Gm-Message-State":"AHYfb5jRytRQgr0n1M/qx8pvY5PHO459f16ZjYKp18GuOzFvRdUOk3Cf\n\t1M66BSJhmYeSWAeXvQU=","X-Received":"by 10.28.135.15 with SMTP id j15mr282704wmd.127.1504032353772;\n\tTue, 29 Aug 2017 11:45:53 -0700 (PDT)","From":"Florian Fainelli ","To":"netdev@vger.kernel.org","Cc":"davem@davemloft.net, opendmb@gmail.com, andrew@lunn.ch,\n\tvivien.didelot@savoirfairelinux.com,\n\tFlorian Fainelli ","Subject":"[PATCH net-next 1/4] net: systemport: Use correct I/O accessors","Date":"Tue, 29 Aug 2017 11:39:42 -0700","Message-Id":"<1504031985-52808-2-git-send-email-f.fainelli@gmail.com>","X-Mailer":"git-send-email 1.9.1","In-Reply-To":"<1504031985-52808-1-git-send-email-f.fainelli@gmail.com>","References":"<1504031985-52808-1-git-send-email-f.fainelli@gmail.com>","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"netdev@vger.kernel.org"},"content":"The SYSTEMPORT driver currently uses __raw_{read,write}l which means\nnative I/O endian. This works correctly for an ARM LE kernel (default)\nbut fails miserably on an ARM BE (BE8) kernel where registers are kept\nlittle endian, so replace uses with {read,write}l_relaxed here which is\nwhat we want because this is all performance sensitive code.\n\nSigned-off-by: Florian Fainelli \n---\n drivers/net/ethernet/broadcom/bcmsysport.c | 12 ++++++------\n 1 file changed, 6 insertions(+), 6 deletions(-)","diff":"diff --git a/drivers/net/ethernet/broadcom/bcmsysport.c b/drivers/net/ethernet/broadcom/bcmsysport.c\nindex b3a21418f511..a7e84292af50 100644\n--- a/drivers/net/ethernet/broadcom/bcmsysport.c\n+++ b/drivers/net/ethernet/broadcom/bcmsysport.c\n@@ -32,13 +32,13 @@\n #define BCM_SYSPORT_IO_MACRO(name, offset) \\\n static inline u32 name##_readl(struct bcm_sysport_priv *priv, u32 off)\t\\\n {\t\t\t\t\t\t\t\t\t\\\n-\tu32 reg = __raw_readl(priv->base + offset + off);\t\t\\\n+\tu32 reg = readl_relaxed(priv->base + offset + off);\t\t\\\n \treturn reg;\t\t\t\t\t\t\t\\\n }\t\t\t\t\t\t\t\t\t\\\n static inline void name##_writel(struct bcm_sysport_priv *priv,\t\t\\\n \t\t\t\t u32 val, u32 off)\t\t\t\\\n {\t\t\t\t\t\t\t\t\t\\\n-\t__raw_writel(val, priv->base + offset + off);\t\t\t\\\n+\twritel_relaxed(val, priv->base + offset + off);\t\t\t\\\n }\t\t\t\t\t\t\t\t\t\\\n \n BCM_SYSPORT_IO_MACRO(intrl2_0, SYS_PORT_INTRL2_0_OFFSET);\n@@ -59,14 +59,14 @@ static inline u32 rdma_readl(struct bcm_sysport_priv *priv, u32 off)\n {\n \tif (priv->is_lite && off >= RDMA_STATUS)\n \t\toff += 4;\n-\treturn __raw_readl(priv->base + SYS_PORT_RDMA_OFFSET + off);\n+\treturn readl_relaxed(priv->base + SYS_PORT_RDMA_OFFSET + off);\n }\n \n static inline void rdma_writel(struct bcm_sysport_priv *priv, u32 val, u32 off)\n {\n \tif (priv->is_lite && off >= RDMA_STATUS)\n \t\toff += 4;\n-\t__raw_writel(val, priv->base + SYS_PORT_RDMA_OFFSET + off);\n+\twritel_relaxed(val, priv->base + SYS_PORT_RDMA_OFFSET + off);\n }\n \n static inline u32 tdma_control_bit(struct bcm_sysport_priv *priv, u32 bit)\n@@ -110,10 +110,10 @@ static inline void dma_desc_set_addr(struct bcm_sysport_priv *priv,\n \t\t\t\t dma_addr_t addr)\n {\n #ifdef CONFIG_PHYS_ADDR_T_64BIT\n-\t__raw_writel(upper_32_bits(addr) & DESC_ADDR_HI_MASK,\n+\twritel_relaxed(upper_32_bits(addr) & DESC_ADDR_HI_MASK,\n \t\t d + DESC_ADDR_HI_STATUS_LEN);\n #endif\n-\t__raw_writel(lower_32_bits(addr), d + DESC_ADDR_LO);\n+\twritel_relaxed(lower_32_bits(addr), d + DESC_ADDR_LO);\n }\n \n static inline void tdma_port_write_desc_addr(struct bcm_sysport_priv *priv,\n","prefixes":["net-next","1/4"]}