{"id":807085,"url":"http://patchwork.ozlabs.org/api/1.0/patches/807085/?format=json","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.0/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<1504003561-6290-18-git-send-email-tien.fong.chee@intel.com>","date":"2017-08-29T10:45:59","name":"[U-Boot,17/19] arm: socfpga: Adding clock frequency info for U-boot","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"994144a2fece5f43569152d1edc19ae25850850c","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/1.0/people/70549/?format=json","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"delegate":{"id":1699,"url":"http://patchwork.ozlabs.org/api/1.0/users/1699/?format=json","username":"marex","first_name":"Marek","last_name":"Vasut","email":"marek.vasut@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1504003561-6290-18-git-send-email-tien.fong.chee@intel.com/mbox/","series":[{"id":345,"url":"http://patchwork.ozlabs.org/api/1.0/series/345/?format=json","date":"2017-08-29T10:45:42","name":"Add FPGA, SDRAM drivers and booting to U-boot","version":1,"mbox":"http://patchwork.ozlabs.org/series/345/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/807085/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xhTLq23qNz9t3w\n\tfor ;\n\tTue, 29 Aug 2017 23:00:53 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 32D4FC21E2C; Tue, 29 Aug 2017 11:35:40 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 20F46C21E2C;\n\tTue, 29 Aug 2017 11:35:34 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid BC996C22056; Tue, 29 Aug 2017 10:46:53 +0000 (UTC)","from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby lists.denx.de (Postfix) with ESMTPS id 9698DC21F2D\n\tfor ; Tue, 29 Aug 2017 10:46:48 +0000 (UTC)","from orsmga005.jf.intel.com ([10.7.209.41])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t29 Aug 2017 03:46:48 -0700","from tfchee-mobl.gar.corp.intel.com (HELO tienfong.fm.intel.com,\n\t) ([10.226.242.65])\n\tby orsmga005.jf.intel.com with ESMTP; 29 Aug 2017 03:46:46 -0700"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.41,444,1498546800\"; d=\"scan'208\";a=\"143176742\"","From":"tien.fong.chee@intel.com","To":"u-boot@lists.denx.de","Date":"Tue, 29 Aug 2017 18:45:59 +0800","Message-Id":"<1504003561-6290-18-git-send-email-tien.fong.chee@intel.com>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1504003561-6290-1-git-send-email-tien.fong.chee@intel.com>","References":"<1504003561-6290-1-git-send-email-tien.fong.chee@intel.com>","Cc":"Marek Vasut , Tien Fong Chee , \n\tChing Liang See ,\n\tTien Fong , \n\tWestergteen Dalon ","Subject":"[U-Boot] [PATCH 17/19] arm: socfpga: Adding clock frequency info\n\tfor U-boot","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"From: Tien Fong Chee \n\nClock frequency info is required in U-boot.\n\nSigned-off-by: Tien Fong Chee \n---\n arch/arm/mach-socfpga/board.c | 6 ++++++\n 1 files changed, 6 insertions(+), 0 deletions(-)","diff":"diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c\nindex 3f2e30a..b7b2c8b 100644\n--- a/arch/arm/mach-socfpga/board.c\n+++ b/arch/arm/mach-socfpga/board.c\n@@ -8,7 +8,10 @@\n \n #include \n #include \n+#include \n #include \n+#include \n+#include \n #include \n \n #include \n@@ -26,6 +29,9 @@ int board_init(void)\n \t/* Address of boot parameters for ATAG (if ATAG is used) */\n \tgd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;\n \n+\t/* configuring the clock based on handoff */\n+\tcm_basic_init(gd->fdt_blob);\n+\n \treturn 0;\n }\n \n","prefixes":["U-Boot","17/19"]}