{"id":807054,"url":"http://patchwork.ozlabs.org/api/1.0/patches/807054/?format=json","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.0/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<1504003561-6290-17-git-send-email-tien.fong.chee@intel.com>","date":"2017-08-29T10:45:58","name":"[U-Boot,16/19] arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"44f494b8d77414ef4058f47e8b8f90fbee0b31b0","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/1.0/people/70549/?format=json","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"delegate":{"id":1699,"url":"http://patchwork.ozlabs.org/api/1.0/users/1699/?format=json","username":"marex","first_name":"Marek","last_name":"Vasut","email":"marek.vasut@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1504003561-6290-17-git-send-email-tien.fong.chee@intel.com/mbox/","series":[{"id":345,"url":"http://patchwork.ozlabs.org/api/1.0/series/345/?format=json","date":"2017-08-29T10:45:42","name":"Add FPGA, SDRAM drivers and booting to U-boot","version":1,"mbox":"http://patchwork.ozlabs.org/series/345/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/807054/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xhRMw729Dz9sP5\n\tfor ;\n\tTue, 29 Aug 2017 21:33:16 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 5CC71C21F2D; Tue, 29 Aug 2017 10:50:00 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id DC177C21EF7;\n\tTue, 29 Aug 2017 10:49:57 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid D7C60C22029; Tue, 29 Aug 2017 10:46:50 +0000 (UTC)","from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby lists.denx.de (Postfix) with ESMTPS id 3103BC21DC0\n\tfor ; Tue, 29 Aug 2017 10:46:46 +0000 (UTC)","from orsmga005.jf.intel.com ([10.7.209.41])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t29 Aug 2017 03:46:45 -0700","from tfchee-mobl.gar.corp.intel.com (HELO tienfong.fm.intel.com,\n\t) ([10.226.242.65])\n\tby orsmga005.jf.intel.com with ESMTP; 29 Aug 2017 03:46:43 -0700"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.41,444,1498546800\"; d=\"scan'208\";a=\"143176730\"","From":"tien.fong.chee@intel.com","To":"u-boot@lists.denx.de","Date":"Tue, 29 Aug 2017 18:45:58 +0800","Message-Id":"<1504003561-6290-17-git-send-email-tien.fong.chee@intel.com>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1504003561-6290-1-git-send-email-tien.fong.chee@intel.com>","References":"<1504003561-6290-1-git-send-email-tien.fong.chee@intel.com>","Cc":"Marek Vasut , Tien Fong Chee , \n\tChing Liang See ,\n\tTien Fong , \n\tWestergteen Dalon ","Subject":"[U-Boot] [PATCH 16/19] arm: socfpga: Enhance Intel SoCFPGA program\n\theader to support Arria 10","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"From: Tien Fong Chee \n\nEnhance preloader header with both additional program length and program\nentry offset attributes, which offset is relative to the start of program\nheader.\n\nSigned-off-by: Tien Fong Chee \n---\n arch/arm/mach-socfpga/include/mach/boot0.h | 9 +++++++--\n 1 files changed, 7 insertions(+), 2 deletions(-)","diff":"diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h b/arch/arm/mach-socfpga/include/mach/boot0.h\nindex 22d9e7f..94480b4 100644\n--- a/arch/arm/mach-socfpga/include/mach/boot0.h\n+++ b/arch/arm/mach-socfpga/include/mach/boot0.h\n@@ -11,8 +11,13 @@\n \t.balignl 64,0xf33db33f;\n \n \t.word\t0x1337c0d3;\t/* SoCFPGA preloader validation word */\n-\t.word\t0xc01df00d;\t/* Version, flags, length */\n-\t.word\t0xcafec0d3;\t/* Checksum, zero-pad */\n+\t.word\t0xc01df00d; /* Header length(2B),flags(1B),version(1B) */\n+#ifndef CONFIG_TARGET_SOCFPGA_GEN5\n+\t.word\t0xfeedface; /* Program length(4B) */\n+\t.word\t0xf00dcafe; /* Program entry offset(4B),relative to */\n+\t\t\t\t\t\t/* the start of program header */\n+#endif\n+\t.word\t0xcafec0d3;\t/* Simple checksum(2B),spare offset(2B) */\n \tnop;\n \n \tb reset;\t\t/* SoCFPGA jumps here */\n","prefixes":["U-Boot","16/19"]}