{"id":807001,"url":"http://patchwork.ozlabs.org/api/1.0/patches/807001/?format=json","project":{"id":37,"url":"http://patchwork.ozlabs.org/api/1.0/projects/37/?format=json","name":"Devicetree Bindings","link_name":"devicetree-bindings","list_id":"devicetree.vger.kernel.org","list_email":"devicetree@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20170829084116.106695-3-liwei213@huawei.com>","date":"2017-08-29T08:41:13","name":"[v3,2/5] dt-bindings: scsi: ufs: add document for hisi-ufs","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":true,"hash":"8f1ec8f87b8ffd8c542c4ac54e55c32e04b4ac11","submitter":{"id":72250,"url":"http://patchwork.ozlabs.org/api/1.0/people/72250/?format=json","name":"liwei (CM)","email":"liwei213@huawei.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170829084116.106695-3-liwei213@huawei.com/mbox/","series":[{"id":325,"url":"http://patchwork.ozlabs.org/api/1.0/series/325/?format=json","date":"2017-08-29T08:41:11","name":"scsi: ufs: add ufs driver code for Hisilicon Hi3660 SoC","version":3,"mbox":"http://patchwork.ozlabs.org/series/325/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/807001/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xhMc66G7Yz9sRV\n\tfor ;\n\tTue, 29 Aug 2017 18:43:34 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751366AbdH2Ilq (ORCPT\n\t);\n\tTue, 29 Aug 2017 04:41:46 -0400","from szxga05-in.huawei.com ([45.249.212.191]:5029 \"EHLO\n\tszxga05-in.huawei.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1750779AbdH2Iln (ORCPT\n\t); Tue, 29 Aug 2017 04:41:43 -0400","from 172.30.72.60 (EHLO DGGEMS409-HUB.china.huawei.com)\n\t([172.30.72.60])\n\tby dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued)\n\twith ESMTP id DGE69517; Tue, 29 Aug 2017 16:41:32 +0800 (CST)","from vm107-89-192.huawei.com (100.107.89.192) by\n\tDGGEMS409-HUB.china.huawei.com (10.3.19.209) with Microsoft SMTP\n\tServer id 14.3.301.0; Tue, 29 Aug 2017 16:41:19 +0800"],"From":"Li Wei ","To":", ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t,\n\t,\n\t, ,\n\t, , ,\n\t, ,\n\t, ","CC":", ","Subject":"[PATCH v3 2/5] dt-bindings: scsi: ufs: add document for hisi-ufs","Date":"Tue, 29 Aug 2017 16:41:13 +0800","Message-ID":"<20170829084116.106695-3-liwei213@huawei.com>","X-Mailer":"git-send-email 2.11.0","In-Reply-To":"<20170829084116.106695-1-liwei213@huawei.com>","References":"<20170829084116.106695-1-liwei213@huawei.com>","MIME-Version":"1.0","Content-Type":"text/plain","X-Originating-IP":"[100.107.89.192]","X-CFilter-Loop":"Reflected","X-Mirapoint-Virus-RAPID-Raw":"score=unknown(0),\n\trefid=str=0001.0A090203.59A528BC.008E, ss=1, re=0.000, recu=0.000,\n\treip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0,\n\tso=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32","X-Mirapoint-Loop-Id":"46925d46b84f73d2059701949ca0cab6","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"},"content":"add ufs node document for Hisilicon\n\nSigned-off-by: Li Wei \n---\n Documentation/devicetree/bindings/ufs/ufs-hisi.txt | 35 ++++++++++++++++++++++\n 1 file changed, 35 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/ufs/ufs-hisi.txt","diff":"diff --git a/Documentation/devicetree/bindings/ufs/ufs-hisi.txt b/Documentation/devicetree/bindings/ufs/ufs-hisi.txt\nnew file mode 100644\nindex 000000000000..cfc84c821d50\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/ufs/ufs-hisi.txt\n@@ -0,0 +1,35 @@\n+* Hisilicon Universal Flash Storage (UFS) Host Controller\n+\n+UFS nodes are defined to describe on-chip UFS hardware macro.\n+Each UFS Host Controller should have its own node.\n+\n+Required properties:\n+- compatible : compatible list, contains one of the following -\n+\t\t\t\"hisilicon,hi3660-ufs\" for hisi ufs host controller\n+\t\t\t present on Hi3660 chipset.\n+- reg : should contain UFS register address space & UFS SYS CTRL register address,\n+- interrupt-parent : interrupt device\n+- interrupts : interrupt number\n+- clocks\t : List of phandle and clock specifier pairs\n+- clock-names : List of clock input name strings sorted in the same\n+\t\t order as the clocks property. \"clk_ref\", \"clk_phy\" is optional\n+\n+Optional properties for board device:\n+- reset-gpio\t\t\t: specifies to reset devices\n+\n+Example:\n+\n+\tufs: ufs@ff3b0000 {\n+\t\tcompatible = \"jedec,ufs-1.1\", \"hisilicon,hi3660-ufs\";\n+\t\t/* 0: HCI standard */\n+\t\t/* 1: UFS SYS CTRL */\n+\t\treg = <0x0 0xff3b0000 0x0 0x1000>,\n+\t\t\t<0x0 0xff3b1000 0x0 0x1000>;\n+\t\tinterrupt-parent = <&gic>;\n+\t\tinterrupts = ;\n+\t\tclocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,\n+\t\t\t<&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;\n+\t\tclock-names = \"clk_ref\", \"clk_phy\";\n+\t\tfreq-table-hz = <0 0>, <0 0>;\n+\t\treset-gpio = <&gpio18 1 0>;\n+\t}\n","prefixes":["v3","2/5"]}