{"id":806632,"url":"http://patchwork.ozlabs.org/api/1.0/patches/806632/?format=json","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.0/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20170828152517.24506-3-jlu@pengutronix.de>","date":"2017-08-28T15:25:17","name":"[2/2] PCI: mvebu: Check DRAM window size","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":false,"hash":"70166f83170904e2af780da2e0bcfc5271114129","submitter":{"id":16217,"url":"http://patchwork.ozlabs.org/api/1.0/people/16217/?format=json","name":"Jan Lübbe","email":"jlu@pengutronix.de"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20170828152517.24506-3-jlu@pengutronix.de/mbox/","series":[{"id":195,"url":"http://patchwork.ozlabs.org/api/1.0/series/195/?format=json","date":"2017-08-28T15:25:17","name":"fix 4GB DRAM window support on mvebu","version":1,"mbox":"http://patchwork.ozlabs.org/series/195/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/806632/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xgwZT2m5wz9sNn\n\tfor ;\n\tTue, 29 Aug 2017 01:25:37 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751270AbdH1PZf (ORCPT );\n\tMon, 28 Aug 2017 11:25:35 -0400","from metis.ext.4.pengutronix.de ([92.198.50.35]:60367 \"EHLO\n\tmetis.ext.4.pengutronix.de\" rhost-flags-OK-OK-OK-OK)\n\tby vger.kernel.org with ESMTP id S1751161AbdH1PZe (ORCPT\n\t); Mon, 28 Aug 2017 11:25:34 -0400","from dude.hi.pengutronix.de ([2001:67c:670:100:1d::7])\n\tby metis.ext.pengutronix.de with esmtps\n\t(TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.84_2)\n\t(envelope-from )\n\tid 1dmLus-00080v-Cb; Mon, 28 Aug 2017 17:25:30 +0200","from jlu by dude.hi.pengutronix.de with local (Exim 4.89)\n\t(envelope-from )\n\tid 1dmLur-0006O5-KI; Mon, 28 Aug 2017 17:25:29 +0200"],"From":"Jan Luebbe ","To":"Gregory Clement ,\n\tAndrew Lunn ,\n\tThomas Petazzoni ,\n\tJason Cooper ","Cc":"linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-kernel@vger.kernel.org, kernel@pengutronix.de,\n\tJan Luebbe ","Subject":"[PATCH 2/2] PCI: mvebu: Check DRAM window size","Date":"Mon, 28 Aug 2017 17:25:17 +0200","Message-Id":"<20170828152517.24506-3-jlu@pengutronix.de>","X-Mailer":"git-send-email 2.11.0","In-Reply-To":"<20170828152517.24506-1-jlu@pengutronix.de>","References":"<20170828152517.24506-1-jlu@pengutronix.de>","X-SA-Exim-Connect-IP":"2001:67c:670:100:1d::7","X-SA-Exim-Mail-From":"jlu@pengutronix.de","X-SA-Exim-Scanned":"No (on metis.ext.pengutronix.de);\n\tSAEximRunCond expanded to false","X-PTX-Original-Recipient":"linux-pci@vger.kernel.org","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"},"content":"The sum of the DRAM windows may exceed 4GB (at least on Armada XP).\nReturn an error in that case.\n\nSigned-off-by: Jan Luebbe \n---\n drivers/pci/host/pci-mvebu.c | 27 ++++++++++++++++++++++-----\n 1 file changed, 22 insertions(+), 5 deletions(-)","diff":"diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c\nindex f353a6eb2f01..5d74af81d104 100644\n--- a/drivers/pci/host/pci-mvebu.c\n+++ b/drivers/pci/host/pci-mvebu.c\n@@ -206,10 +206,10 @@ static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)\n * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks\n * WIN[0-3] -> DRAM bank[0-3]\n */\n-static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)\n+static int mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)\n {\n \tconst struct mbus_dram_target_info *dram;\n-\tu32 size;\n+\tu64 size;\n \tint i;\n \n \tdram = mv_mbus_dram_info();\n@@ -252,19 +252,32 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)\n \tif ((size & (size - 1)) != 0)\n \t\tsize = 1 << fls(size);\n \n+\tif (size > 0x100000000) {\n+\t\tdev_err(&port->pcie->pdev->dev,\n+\t\t\t\"Could not configure DRAM window (too large): 0x%llx\\n\",\n+\t\t\tsize);\n+\n+\t\treturn -EINVAL;\n+\t}\n+\n \t/* Setup BAR[1] to all DRAM banks. */\n \tmvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1));\n \tmvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));\n \tmvebu_writel(port, ((size - 1) & 0xffff0000) | 1,\n \t\t PCIE_BAR_CTRL_OFF(1));\n+\n+\treturn 0;\n }\n \n-static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)\n+static int mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)\n {\n \tu32 cmd, mask;\n+\tint ret;\n \n \t/* Point PCIe unit MBUS decode windows to DRAM space. */\n-\tmvebu_pcie_setup_wins(port);\n+\tret = mvebu_pcie_setup_wins(port);\n+\tif (ret)\n+\t\treturn ret;\n \n \t/* Master + slave enable. */\n \tcmd = mvebu_readl(port, PCIE_CMD_OFF);\n@@ -277,6 +290,8 @@ static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)\n \tmask = mvebu_readl(port, PCIE_MASK_OFF);\n \tmask |= PCIE_MASK_ENABLE_INTS;\n \tmvebu_writel(port, mask, PCIE_MASK_OFF);\n+\n+\treturn 0;\n }\n \n static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,\n@@ -882,7 +897,9 @@ static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys)\n \n \t\tif (!port->base)\n \t\t\tcontinue;\n-\t\tmvebu_pcie_setup_hw(port);\n+\t\terr = mvebu_pcie_setup_hw(port);\n+\t\tif (err)\n+\t\t\treturn 0;\n \t}\n \n \treturn 1;\n","prefixes":["2/2"]}