{"id":806554,"url":"http://patchwork.ozlabs.org/api/1.0/patches/806554/?format=json","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.0/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20170828121638.13751-1-thomas.petazzoni@free-electrons.com>","date":"2017-08-28T12:16:38","name":"[U-Boot] serial: serial_sh: take into account port->clk_mode for SH7785/7786","commit_ref":null,"pull_url":null,"state":"deferred","archived":false,"hash":"8a146e27bdb1047da3f76f969775153802e6fe09","submitter":{"id":2230,"url":"http://patchwork.ozlabs.org/api/1.0/people/2230/?format=json","name":"Thomas Petazzoni","email":"thomas.petazzoni@free-electrons.com"},"delegate":{"id":3651,"url":"http://patchwork.ozlabs.org/api/1.0/users/3651/?format=json","username":"trini","first_name":"Tom","last_name":"Rini","email":"trini@ti.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20170828121638.13751-1-thomas.petazzoni@free-electrons.com/mbox/","series":[{"id":154,"url":"http://patchwork.ozlabs.org/api/1.0/series/154/?format=json","date":"2017-08-28T12:16:38","name":"[U-Boot] serial: serial_sh: take into account port->clk_mode for SH7785/7786","version":1,"mbox":"http://patchwork.ozlabs.org/series/154/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/806554/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xgrNj28W6z9sMN\n\tfor ;\n\tMon, 28 Aug 2017 22:16:53 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid E8E5CC21DAB; Mon, 28 Aug 2017 12:16:44 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 3D594C21DA4;\n\tMon, 28 Aug 2017 12:16:42 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 22192C21DA4; Mon, 28 Aug 2017 12:16:41 +0000 (UTC)","from mail.free-electrons.com (mail.free-electrons.com [62.4.15.54])\n\tby lists.denx.de (Postfix) with ESMTP id CF47CC21C54\n\tfor ; Mon, 28 Aug 2017 12:16:40 +0000 (UTC)","by mail.free-electrons.com (Postfix, from userid 110)\n\tid 9334320A31; Mon, 28 Aug 2017 14:16:39 +0200 (CEST)","from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr\n\t[90.63.216.87])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id 6B6102096D;\n\tMon, 28 Aug 2017 14:16:39 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.0 required=5.0 tests=none autolearn=unavailable\n\tautolearn_force=no version=3.4.0","From":"Thomas Petazzoni ","To":"Hiroyuki Yokoyama ,\n\tNobuhiro Iwamatsu ,\n\tVladimir Zapolskiy , u-boot@lists.denx.de","Date":"Mon, 28 Aug 2017 14:16:38 +0200","Message-Id":"<20170828121638.13751-1-thomas.petazzoni@free-electrons.com>","X-Mailer":"git-send-email 2.9.4","Cc":"Thomas Petazzoni ","Subject":"[U-Boot] [PATCH] serial: serial_sh: take into account\n\tport->clk_mode for SH7785/7786","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"In the SH7785/SH7786 case, the SCSCR value is harcoded to be 0x3a,\nwhich means bits CKE1/CKE0 have the value 10b. This tells the SCIF\nthat the \"External clock/SCIF_SCK pin functions as clock input\".\n\nHowever, this is not the case in all designs, and it's the purpose of\nthe clk_mode = EXT_CLK to indicate such a setting.\n\nIn order for the serial_sh driver to work on a SH7786 platform that\ndoes not use SCIF_SCK as a clock input, we have to adjust the\nSCSCR_INIT value, to have CKE1/CKE0 set to 00b. This is similar to\nwhat is done for other SH platforms.\n\nSigned-off-by: Thomas Petazzoni \n---\n drivers/serial/serial_sh.h | 3 ++-\n 1 file changed, 2 insertions(+), 1 deletion(-)","diff":"diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h\nindex 4d27122..d7bbd1a 100644\n--- a/drivers/serial/serial_sh.h\n+++ b/drivers/serial/serial_sh.h\n@@ -184,7 +184,8 @@ struct uart_port {\n # define SCSPTR4\t0xffee0024\t/* 16 bit SCIF */\n # define SCSPTR5\t0xffef0024\t/* 16 bit SCIF */\n # define SCIF_ORER\t0x0001\t\t/* Overrun error bit */\n-# define SCSCR_INIT(port)\t0x3a\t/* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */\n+# define SCSCR_INIT(port)\t(port->clk_mode == EXT_CLK ? 0x3a : 0x38)\n+\t\t\t\t/* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */\n #elif defined(CONFIG_CPU_SH7201) || \\\n \tdefined(CONFIG_CPU_SH7203) || \\\n \tdefined(CONFIG_CPU_SH7206) || \\\n","prefixes":["U-Boot"]}