{"id":806475,"url":"http://patchwork.ozlabs.org/api/1.0/patches/806475/?format=json","project":{"id":38,"url":"http://patchwork.ozlabs.org/api/1.0/projects/38/?format=json","name":"Linux PWM development","link_name":"linux-pwm","list_id":"linux-pwm.vger.kernel.org","list_email":"linux-pwm@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<1503914654-19963-3-git-send-email-fabrice.gasnier@st.com>","date":"2017-08-28T10:04:07","name":"[RESEND,v3,2/9] mfd: Add STM32 LPTimer driver","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"2f28392f7308556b08e5a159cbb8130a35074776","submitter":{"id":65902,"url":"http://patchwork.ozlabs.org/api/1.0/people/65902/?format=json","name":"Fabrice Gasnier","email":"fabrice.gasnier@st.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pwm/patch/1503914654-19963-3-git-send-email-fabrice.gasnier@st.com/mbox/","series":[{"id":122,"url":"http://patchwork.ozlabs.org/api/1.0/series/122/?format=json","date":"2017-08-28T10:04:06","name":"Add STM32 LPTimer: PWM, trigger and counter","version":3,"mbox":"http://patchwork.ozlabs.org/series/122/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/806475/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pwm-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xgnVs51Mrz9rxm\n\tfor ;\n\tMon, 28 Aug 2017 20:07:01 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751886AbdH1KGw (ORCPT );\n\tMon, 28 Aug 2017 06:06:52 -0400","from mx08-00178001.pphosted.com ([91.207.212.93]:26271 \"EHLO\n\tmx07-00178001.pphosted.com\" rhost-flags-OK-OK-OK-FAIL)\n\tby vger.kernel.org with ESMTP id S1751549AbdH1KFV (ORCPT\n\t); Mon, 28 Aug 2017 06:05:21 -0400","from pps.filterd (m0046660.ppops.net [127.0.0.1])\n\tby mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv7SA3phl005009; Mon, 28 Aug 2017 12:04:38 +0200","from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35])\n\tby mx08-.pphosted.com with ESMTP id 2cjx459nrn-1\n\t(version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT);\n\tMon, 28 Aug 2017 12:04:38 +0200","from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9])\n\tby beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 1A4A13D;\n\tMon, 28 Aug 2017 10:04:37 +0000 (GMT)","from Webmail-eu.st.com (sfhdag5node3.st.com [10.75.127.15])\n\tby zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id DCCB52064;\n\tMon, 28 Aug 2017 10:04:36 +0000 (GMT)","from localhost (10.75.127.48) by SFHDAG5NODE3.st.com (10.75.127.15)\n\twith Microsoft SMTP Server (TLS) id 15.0.1178.4;\n\tMon, 28 Aug 2017 12:04:36 +0200"],"From":"Fabrice Gasnier ","To":", ,\n\t, , ","CC":", ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t","Subject":"[RESEND PATCH v3 2/9] mfd: Add STM32 LPTimer driver","Date":"Mon, 28 Aug 2017 12:04:07 +0200","Message-ID":"<1503914654-19963-3-git-send-email-fabrice.gasnier@st.com>","X-Mailer":"git-send-email 1.9.1","In-Reply-To":"<1503914654-19963-1-git-send-email-fabrice.gasnier@st.com>","References":"<1503914654-19963-1-git-send-email-fabrice.gasnier@st.com>","MIME-Version":"1.0","Content-Type":"text/plain","X-Originating-IP":"[10.75.127.48]","X-ClientProxiedBy":"SFHDAG5NODE2.st.com (10.75.127.14) To SFHDAG5NODE3.st.com\n\t(10.75.127.15)","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-08-28_06:, , signatures=0","Sender":"linux-pwm-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pwm@vger.kernel.org"},"content":"STM32 Low-Power Timer hardware block can be used for:\n- PWM generation\n- IIO trigger (in sync with PWM)\n- IIO quadrature encoder counter\nPWM and IIO timer configuration are mixed in the same registers so\nwe need a multi fonction driver to be able to share those registers.\n\nSigned-off-by: Fabrice Gasnier \n---\nChanges in v2:\n- Lee's remarks: various comments, max register define, s/Low Power/Low-Power,\n clock name, removed reset, add kernel doc for stm32_lptimer struct\n---\n drivers/mfd/Kconfig | 14 +++++\n drivers/mfd/Makefile | 1 +\n drivers/mfd/stm32-lptimer.c | 107 ++++++++++++++++++++++++++++++++++++++\n include/linux/mfd/stm32-lptimer.h | 62 ++++++++++++++++++++++\n 4 files changed, 184 insertions(+)\n create mode 100644 drivers/mfd/stm32-lptimer.c\n create mode 100644 include/linux/mfd/stm32-lptimer.h","diff":"diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig\nindex 94ad2c1..fe76db9 100644\n--- a/drivers/mfd/Kconfig\n+++ b/drivers/mfd/Kconfig\n@@ -1723,6 +1723,20 @@ config MFD_STW481X\n \t in various ST Microelectronics and ST-Ericsson embedded\n \t Nomadik series.\n \n+config MFD_STM32_LPTIMER\n+\ttristate \"Support for STM32 Low-Power Timer\"\n+\tdepends on (ARCH_STM32 && OF) || COMPILE_TEST\n+\tselect MFD_CORE\n+\tselect REGMAP\n+\tselect REGMAP_MMIO\n+\thelp\n+\t Select this option to enable STM32 Low-Power Timer driver\n+\t used for PWM, IIO Trigger, IIO Encoder and Counter. Shared\n+\t resources are also dealt with here.\n+\n+\t To compile this driver as a module, choose M here: the\n+\t module will be called stm32-lptimer.\n+\n config MFD_STM32_TIMERS\n \ttristate \"Support for STM32 Timers\"\n \tdepends on (ARCH_STM32 && OF) || COMPILE_TEST\ndiff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile\nindex 080793b..b80b1a3 100644\n--- a/drivers/mfd/Makefile\n+++ b/drivers/mfd/Makefile\n@@ -221,5 +221,6 @@ obj-$(CONFIG_MFD_MT6397)\t+= mt6397-core.o\n obj-$(CONFIG_MFD_ALTERA_A10SR)\t+= altera-a10sr.o\n obj-$(CONFIG_MFD_SUN4I_GPADC)\t+= sun4i-gpadc.o\n \n+obj-$(CONFIG_MFD_STM32_LPTIMER)\t+= stm32-lptimer.o\n obj-$(CONFIG_MFD_STM32_TIMERS) \t+= stm32-timers.o\n obj-$(CONFIG_MFD_MXS_LRADC) += mxs-lradc.o\ndiff --git a/drivers/mfd/stm32-lptimer.c b/drivers/mfd/stm32-lptimer.c\nnew file mode 100644\nindex 0000000..075330a\n--- /dev/null\n+++ b/drivers/mfd/stm32-lptimer.c\n@@ -0,0 +1,107 @@\n+/*\n+ * STM32 Low-Power Timer parent driver.\n+ *\n+ * Copyright (C) STMicroelectronics 2017\n+ *\n+ * Author: Fabrice Gasnier \n+ *\n+ * Inspired by Benjamin Gaignard's stm32-timers driver\n+ *\n+ * License terms: GNU General Public License (GPL), version 2\n+ */\n+\n+#include \n+#include \n+#include \n+\n+#define STM32_LPTIM_MAX_REGISTER\t0x3fc\n+\n+static const struct regmap_config stm32_lptimer_regmap_cfg = {\n+\t.reg_bits = 32,\n+\t.val_bits = 32,\n+\t.reg_stride = sizeof(u32),\n+\t.max_register = STM32_LPTIM_MAX_REGISTER,\n+};\n+\n+static int stm32_lptimer_detect_encoder(struct stm32_lptimer *ddata)\n+{\n+\tu32 val;\n+\tint ret;\n+\n+\t/*\n+\t * Quadrature encoder mode bit can only be written and read back when\n+\t * Low-Power Timer supports it.\n+\t */\n+\tret = regmap_update_bits(ddata->regmap, STM32_LPTIM_CFGR,\n+\t\t\t\t STM32_LPTIM_ENC, STM32_LPTIM_ENC);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_read(ddata->regmap, STM32_LPTIM_CFGR, &val);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_update_bits(ddata->regmap, STM32_LPTIM_CFGR,\n+\t\t\t\t STM32_LPTIM_ENC, 0);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tddata->has_encoder = !!(val & STM32_LPTIM_ENC);\n+\n+\treturn 0;\n+}\n+\n+static int stm32_lptimer_probe(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct stm32_lptimer *ddata;\n+\tstruct resource *res;\n+\tvoid __iomem *mmio;\n+\tint ret;\n+\n+\tddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);\n+\tif (!ddata)\n+\t\treturn -ENOMEM;\n+\n+\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tmmio = devm_ioremap_resource(dev, res);\n+\tif (IS_ERR(mmio))\n+\t\treturn PTR_ERR(mmio);\n+\n+\tddata->regmap = devm_regmap_init_mmio_clk(dev, \"mux\", mmio,\n+\t\t\t\t\t\t &stm32_lptimer_regmap_cfg);\n+\tif (IS_ERR(ddata->regmap))\n+\t\treturn PTR_ERR(ddata->regmap);\n+\n+\tddata->clk = devm_clk_get(dev, NULL);\n+\tif (IS_ERR(ddata->clk))\n+\t\treturn PTR_ERR(ddata->clk);\n+\n+\tret = stm32_lptimer_detect_encoder(ddata);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tplatform_set_drvdata(pdev, ddata);\n+\n+\treturn devm_of_platform_populate(&pdev->dev);\n+}\n+\n+static const struct of_device_id stm32_lptimer_of_match[] = {\n+\t{ .compatible = \"st,stm32-lptimer\", },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, stm32_lptimer_of_match);\n+\n+static struct platform_driver stm32_lptimer_driver = {\n+\t.probe = stm32_lptimer_probe,\n+\t.driver = {\n+\t\t.name = \"stm32-lptimer\",\n+\t\t.of_match_table = stm32_lptimer_of_match,\n+\t},\n+};\n+module_platform_driver(stm32_lptimer_driver);\n+\n+MODULE_AUTHOR(\"Fabrice Gasnier \");\n+MODULE_DESCRIPTION(\"STMicroelectronics STM32 Low-Power Timer\");\n+MODULE_ALIAS(\"platform:stm32-lptimer\");\n+MODULE_LICENSE(\"GPL v2\");\ndiff --git a/include/linux/mfd/stm32-lptimer.h b/include/linux/mfd/stm32-lptimer.h\nnew file mode 100644\nindex 0000000..77c7cf4\n--- /dev/null\n+++ b/include/linux/mfd/stm32-lptimer.h\n@@ -0,0 +1,62 @@\n+/*\n+ * STM32 Low-Power Timer parent driver.\n+ *\n+ * Copyright (C) STMicroelectronics 2017\n+ *\n+ * Author: Fabrice Gasnier \n+ *\n+ * Inspired by Benjamin Gaignard's stm32-timers driver\n+ *\n+ * License terms: GNU General Public License (GPL), version 2\n+ */\n+\n+#ifndef _LINUX_STM32_LPTIMER_H_\n+#define _LINUX_STM32_LPTIMER_H_\n+\n+#include \n+#include \n+\n+#define STM32_LPTIM_ISR\t\t0x00\t/* Interrupt and Status Reg */\n+#define STM32_LPTIM_ICR\t\t0x04\t/* Interrupt Clear Reg */\n+#define STM32_LPTIM_IER\t\t0x08\t/* Interrupt Enable Reg */\n+#define STM32_LPTIM_CFGR\t0x0C\t/* Configuration Reg */\n+#define STM32_LPTIM_CR\t\t0x10\t/* Control Reg */\n+#define STM32_LPTIM_CMP\t\t0x14\t/* Compare Reg */\n+#define STM32_LPTIM_ARR\t\t0x18\t/* Autoreload Reg */\n+#define STM32_LPTIM_CNT\t\t0x1C\t/* Counter Reg */\n+\n+/* STM32_LPTIM_ISR - bit fields */\n+#define STM32_LPTIM_CMPOK_ARROK\t\tGENMASK(4, 3)\n+#define STM32_LPTIM_ARROK\t\tBIT(4)\n+#define STM32_LPTIM_CMPOK\t\tBIT(3)\n+\n+/* STM32_LPTIM_ICR - bit fields */\n+#define STM32_LPTIM_CMPOKCF_ARROKCF\tGENMASK(4, 3)\n+\n+/* STM32_LPTIM_CR - bit fields */\n+#define STM32_LPTIM_CNTSTRT\tBIT(2)\n+#define STM32_LPTIM_ENABLE\tBIT(0)\n+\n+/* STM32_LPTIM_CFGR - bit fields */\n+#define STM32_LPTIM_ENC\t\tBIT(24)\n+#define STM32_LPTIM_COUNTMODE\tBIT(23)\n+#define STM32_LPTIM_WAVPOL\tBIT(21)\n+#define STM32_LPTIM_PRESC\tGENMASK(11, 9)\n+#define STM32_LPTIM_CKPOL\tGENMASK(2, 1)\n+\n+/* STM32_LPTIM_ARR */\n+#define STM32_LPTIM_MAX_ARR\t0xFFFF\n+\n+/**\n+ * struct stm32_lptimer - STM32 Low-Power Timer data assigned by parent device\n+ * @clk: clock reference for this instance\n+ * @regmap: register map reference for this instance\n+ * @has_encoder: indicates this Low-Power Timer supports encoder mode\n+ */\n+struct stm32_lptimer {\n+\tstruct clk *clk;\n+\tstruct regmap *regmap;\n+\tbool has_encoder;\n+};\n+\n+#endif\n","prefixes":["RESEND","v3","2/9"]}