{"id":806439,"url":"http://patchwork.ozlabs.org/api/1.0/patches/806439/?format=json","project":{"id":2,"url":"http://patchwork.ozlabs.org/api/1.0/projects/2/?format=json","name":"Linux PPC development","link_name":"linuxppc-dev","list_id":"linuxppc-dev.lists.ozlabs.org","list_email":"linuxppc-dev@lists.ozlabs.org","web_url":"https://github.com/linuxppc/wiki/wiki","scm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git","webscm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/"},"msgid":"<20170828083544.16514-1-aneesh.kumar@linux.vnet.ibm.com>","date":"2017-08-28T08:35:44","name":"[v2] powerpc/mm/cxl: Add barrier when setting mm cpumask","commit_ref":"22259a6e800cdb8e06e65432fcd019983214be0c","pull_url":null,"state":"accepted","archived":false,"hash":"1b82647d126bb1a8fce370f9959b74fd083cc877","submitter":{"id":664,"url":"http://patchwork.ozlabs.org/api/1.0/people/664/?format=json","name":"Aneesh Kumar K.V","email":"aneesh.kumar@linux.vnet.ibm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20170828083544.16514-1-aneesh.kumar@linux.vnet.ibm.com/mbox/","series":[{"id":104,"url":"http://patchwork.ozlabs.org/api/1.0/series/104/?format=json","date":"2017-08-28T08:35:44","name":"[v2] powerpc/mm/cxl: Add barrier when setting mm cpumask","version":2,"mbox":"http://patchwork.ozlabs.org/series/104/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/806439/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xglWT6FYMz9sNq\n\tfor ;\n\tMon, 28 Aug 2017 18:37:25 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xglWT5M6WzDq5b\n\tfor ;\n\tMon, 28 Aug 2017 18:37:25 +1000 (AEST)","from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n\t[148.163.158.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xglTt3NwVzDq5b\n\tfor ;\n\tMon, 28 Aug 2017 18:36:02 +1000 (AEST)","from pps.filterd (m0098421.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv7S8YG2L012392\n\tfor ; Mon, 28 Aug 2017 04:35:59 -0400","from e33.co.us.ibm.com (e33.co.us.ibm.com [32.97.110.151])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2cmbmxjebn-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor ; Mon, 28 Aug 2017 04:35:59 -0400","from localhost\n\tby e33.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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Violators will be prosecuted; \n\tMon, 28 Aug 2017 02:35:55 -0600","from b03ledav004.gho.boulder.ibm.com\n\t(b03ledav004.gho.boulder.ibm.com [9.17.130.235])\n\tby b03cxnp08027.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with\n\tESMTP id v7S8Ztvd65274060; Mon, 28 Aug 2017 01:35:55 -0700","from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 4B46F78038;\n\tMon, 28 Aug 2017 02:35:55 -0600 (MDT)","from skywalker.in.ibm.com (unknown [9.124.35.86])\n\tby b03ledav004.gho.boulder.ibm.com (Postfix) with ESMTP id 85F037803F;\n\tMon, 28 Aug 2017 02:35:53 -0600 (MDT)"],"From":"\"Aneesh Kumar K.V\" ","To":"benh@kernel.crashing.org, paulus@samba.org, mpe@ellerman.id.au","Subject":"[PATCH v2] powerpc/mm/cxl: Add barrier when setting mm cpumask","Date":"Mon, 28 Aug 2017 14:05:44 +0530","X-Mailer":"git-send-email 2.13.5","X-TM-AS-GCONF":"00","x-cbid":"17082808-0008-0000-0000-0000087C4FE4","X-IBM-SpamModules-Scores":"","X-IBM-SpamModules-Versions":"BY=3.00007626; HX=3.00000241; KW=3.00000007;\n\tPH=3.00000004; SC=3.00000225; SDB=6.00908725; UDB=6.00455661;\n\tIPR=6.00688965; \n\tBA=6.00005555; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009;\n\tZB=6.00000000; \n\tZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00016895;\n\tXFM=3.00000015; UTC=2017-08-28 08:35:57","X-IBM-AV-DETECTION":"SAVI=unused REMOTE=unused XFE=unused","x-cbparentid":"17082808-0009-0000-0000-000043BDE742","Message-Id":"<20170828083544.16514-1-aneesh.kumar@linux.vnet.ibm.com>","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-08-28_04:, , signatures=0","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=0\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1708280137","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linuxppc-dev@lists.ozlabs.org,\n\t\"Aneesh Kumar K.V\" ,\n\tAndrew Donnellan ","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"},"content":"We need to add memory barrier so that the page table walk doesn't happen\nbefore the cpumask is set and made visible to the other cpus. We need\nto use a sync here instead of lwsync because lwsync is not sufficient for\nstore/load ordering.\n\nWe also need to add an if (mm) check so that we do the right thing when called\nwith a kernel context. For kernel context, we have mm = NULL. W.r.t kernel\naddress we can skip setting the mm cpumask.\n\nFixes: 0f4bc0932e (\"powerpc/mm/cxl: Add the fault handling cpu to mm cpumask\")\nCc: Andrew Donnellan \nReported-by: Benjamin Herrenschmidt \nReported-by: Dan Carpenter \nSigned-off-by: Aneesh Kumar K.V \n---\n drivers/misc/cxl/fault.c | 14 ++++++++++++--\n 1 file changed, 12 insertions(+), 2 deletions(-)","diff":"diff --git a/drivers/misc/cxl/fault.c b/drivers/misc/cxl/fault.c\nindex ab507e4ed69b..f17f72ea0545 100644\n--- a/drivers/misc/cxl/fault.c\n+++ b/drivers/misc/cxl/fault.c\n@@ -141,9 +141,19 @@ int cxl_handle_mm_fault(struct mm_struct *mm, u64 dsisr, u64 dar)\n \t/*\n \t * Add the fault handling cpu to task mm cpumask so that we\n \t * can do a safe lockless page table walk when inserting the\n-\t * hash page table entry.\n+\t * hash page table entry. This function get called with a\n+\t * valid mm for user space addresses. Hence using the if (mm)\n+\t * check is sufficient here.\n \t */\n-\tcpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));\n+\tif (mm && !cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm))) {\n+\t\tcpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));\n+\t\t/*\n+\t\t * We need to make sure we walk the table only after\n+\t\t * we update the cpumask. The other side of the barrier\n+\t\t * is explained in serialize_against_pte_lookup()\n+\t\t */\n+\t\tsmp_mb();\n+\t}\n \tif ((result = copro_handle_mm_fault(mm, dar, dsisr, &flt))) {\n \t\tpr_devel(\"copro_handle_mm_fault failed: %#x\\n\", result);\n \t\treturn result;\n","prefixes":["v2"]}