{"id":806339,"url":"http://patchwork.ozlabs.org/api/1.0/patches/806339/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20170828015654.2530-5-Sergio.G.DelReal@gmail.com>","date":"2017-08-28T01:56:44","name":"[04/14] hvf: add fields to CPUState and CPUX86State; add definitions","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"decd5f7ee9578777ad15129ccb1fddec14f3c2e9","submitter":{"id":70675,"url":"http://patchwork.ozlabs.org/api/1.0/people/70675/?format=json","name":"Sergio Andres Gomez Del Real","email":"sergio.g.delreal@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170828015654.2530-5-Sergio.G.DelReal@gmail.com/mbox/","series":[{"id":56,"url":"http://patchwork.ozlabs.org/api/1.0/series/56/?format=json","date":"2017-08-28T01:56:40","name":"add support for Hypervisor.framework in QEMU","version":1,"mbox":"http://patchwork.ozlabs.org/series/56/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/806339/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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add definitions","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Sergio Andres Gomez Del Real ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"This commit adds some fields specific to hvf in CPUState and\nCPUX86State. It also adds some handy #defines.\n\nSigned-off-by: Sergio Andres Gomez Del Real \n---\n include/qom/cpu.h | 8 ++++++++\n target/i386/cpu.h | 23 +++++++++++++++++++++++\n 2 files changed, 31 insertions(+)","diff":"diff --git a/include/qom/cpu.h b/include/qom/cpu.h\nindex 25eefea7ab..c46eb61240 100644\n--- a/include/qom/cpu.h\n+++ b/include/qom/cpu.h\n@@ -407,6 +407,14 @@ struct CPUState {\n * unnecessary flushes.\n */\n uint16_t pending_tlb_flush;\n+\n+ // HVF\n+ bool hvf_vcpu_dirty;\n+ uint64_t hvf_fd; // fd of vcpu created by HVF\n+ // Supporting data structures for VMCS capabilities\n+ // and x86 emulation state\n+ struct hvf_vcpu_caps* hvf_caps;\n+ struct hvf_x86_state* hvf_x86;\n };\n \n QTAILQ_HEAD(CPUTailQ, CPUState);\ndiff --git a/target/i386/cpu.h b/target/i386/cpu.h\nindex 051867399b..7d90f08b98 100644\n--- a/target/i386/cpu.h\n+++ b/target/i386/cpu.h\n@@ -82,15 +82,19 @@\n #define R_GS 5\n \n /* segment descriptor fields */\n+#define DESC_G_SHIFT 23\n #define DESC_G_MASK (1 << 23)\n #define DESC_B_SHIFT 22\n #define DESC_B_MASK (1 << DESC_B_SHIFT)\n #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */\n #define DESC_L_MASK (1 << DESC_L_SHIFT)\n+#define DESC_AVL_SHIFT 20\n #define DESC_AVL_MASK (1 << 20)\n+#define DESC_P_SHIFT 15\n #define DESC_P_MASK (1 << 15)\n #define DESC_DPL_SHIFT 13\n #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)\n+#define DESC_S_SHIFT 12\n #define DESC_S_MASK (1 << 12)\n #define DESC_TYPE_SHIFT 8\n #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT)\n@@ -631,6 +635,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];\n #define CPUID_7_0_EBX_AVX512BW (1U << 30) /* AVX-512 Byte and Word Instructions */\n #define CPUID_7_0_EBX_AVX512VL (1U << 31) /* AVX-512 Vector Length Extensions */\n \n+#define CPUID_7_0_ECX_AVX512BMI (1U << 1)\n #define CPUID_7_0_ECX_VBMI (1U << 1) /* AVX-512 Vector Byte Manipulation Instrs */\n #define CPUID_7_0_ECX_UMIP (1U << 2)\n #define CPUID_7_0_ECX_PKU (1U << 3)\n@@ -806,6 +811,20 @@ typedef struct SegmentCache {\n float64 _d_##n[(bits)/64]; \\\n }\n \n+typedef union {\n+ uint8_t _b[16];\n+ uint16_t _w[8];\n+ uint32_t _l[4];\n+ uint64_t _q[2];\n+} XMMReg;\n+\n+typedef union {\n+ uint8_t _b[32];\n+ uint16_t _w[16];\n+ uint32_t _l[8];\n+ uint64_t _q[4];\n+} YMMReg;\n+\n typedef MMREG_UNION(ZMMReg, 512) ZMMReg;\n typedef MMREG_UNION(MMXReg, 64) MMXReg;\n \n@@ -1041,7 +1060,11 @@ typedef struct CPUX86State {\n ZMMReg xmm_t0;\n MMXReg mmx_t0;\n \n+ XMMReg ymmh_regs[CPU_NB_REGS];\n+\n uint64_t opmask_regs[NB_OPMASK_REGS];\n+ YMMReg zmmh_regs[CPU_NB_REGS];\n+ ZMMReg hi16_zmm_regs[CPU_NB_REGS];\n \n /* sysenter registers */\n uint32_t sysenter_cs;\n","prefixes":["04/14"]}