{"id":806295,"url":"http://patchwork.ozlabs.org/api/1.0/patches/806295/?format=json","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/1.0/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"","date":"2017-08-27T18:04:03","name":"[i386] : Fix PR 81995, error: unrecognizable insn","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"bcb4543b0b5fd7534cec247a5aad3a6f0d1740ff","submitter":{"id":808,"url":"http://patchwork.ozlabs.org/api/1.0/people/808/?format=json","name":"Uros Bizjak","email":"ubizjak@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/CAFULd4aUAV_aNLnP-wV1ooz1HSh6+zez_+Qm1gkYpLdqkUbCUw@mail.gmail.com/mbox/","series":[{"id":37,"url":"http://patchwork.ozlabs.org/api/1.0/series/37/?format=json","date":"2017-08-27T18:04:03","name":"[i386] : Fix PR 81995, error: unrecognizable insn","version":1,"mbox":"http://patchwork.ozlabs.org/series/37/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/806295/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; 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boundary=\"001a1143ef28ecc0a10557c00017\""},"content":"Matched operands should also have matched predicate...\n\n2017-08-27 Uros Bizjak \n\n PR target/81995\n * config/i386/i386.md (*): Change operand 2\n predicate to register_operand. Reorder operands.\n (*btr): Ditto.\n (*_mask): Change operand 3 predicate to register_operand.\n (*btr_mask): Ditto.\n\ntestsuite/ChangeLog:\n\n2017-08-27 Uros Bizjak \n\n PR target/81995\n * gcc.target/i386/pr46091-4.c: Add -mregparm=2 for 32bit targets.\n * gcc.target/i386/pr46091-4a.c: Ditto.\n\nBootstrapped and regression tested on x86_64-linux-gnu {,-m32}.\n\nCommitted to mainline SVN.\n\nUros.","diff":"Index: config/i386/i386.md\n===================================================================\n--- config/i386/i386.md\t(revision 251368)\n+++ config/i386/i386.md\t(working copy)\n@@ -11011,11 +11011,11 @@\n [(set (match_operand:SWI48 0 \"register_operand\" \"=r\")\n \t(any_or:SWI48\n \t (ashift:SWI48 (const_int 1)\n-\t\t\t(match_operand:QI 1 \"register_operand\" \"r\"))\n-\t (match_operand:SWI48 2 \"nonimmediate_operand\" \"0\")))\n+\t\t\t(match_operand:QI 2 \"register_operand\" \"r\"))\n+\t (match_operand:SWI48 1 \"register_operand\" \"0\")))\n (clobber (reg:CC FLAGS_REG))]\n \"TARGET_USE_BT\"\n- \"{}\\t{%1, %0|%0, %1}\"\n+ \"{}\\t{%2, %0|%0, %2}\"\n [(set_attr \"type\" \"alu1\")\n (set_attr \"prefix_0f\" \"1\")\n (set_attr \"znver1_decode\" \"double\")\n@@ -11031,7 +11031,7 @@\n \t (and:SI\n \t\t(match_operand:SI 1 \"register_operand\")\n \t\t(match_operand:SI 2 \"const_int_operand\")) 0))\n-\t (match_operand:SWI48 3 \"nonimmediate_operand\")))\n+\t (match_operand:SWI48 3 \"register_operand\")))\n (clobber (reg:CC FLAGS_REG))]\n \"(INTVAL (operands[2]) & (GET_MODE_BITSIZE (mode)-1))\n == GET_MODE_BITSIZE (mode)-1\n@@ -11051,11 +11051,11 @@\n [(set (match_operand:SWI48 0 \"register_operand\" \"=r\")\n \t(and:SWI48\n \t (rotate:SWI48 (const_int -2)\n-\t\t\t(match_operand:QI 1 \"register_operand\" \"r\"))\n-\t(match_operand:SWI48 2 \"nonimmediate_operand\" \"0\")))\n+\t\t\t(match_operand:QI 2 \"register_operand\" \"r\"))\n+\t(match_operand:SWI48 1 \"register_operand\" \"0\")))\n (clobber (reg:CC FLAGS_REG))]\n \"TARGET_USE_BT\"\n- \"btr{}\\t{%1, %0|%0, %1}\"\n+ \"btr{}\\t{%2, %0|%0, %2}\"\n [(set_attr \"type\" \"alu1\")\n (set_attr \"prefix_0f\" \"1\")\n (set_attr \"znver1_decode\" \"double\")\n@@ -11071,7 +11071,7 @@\n \t (and:SI\n \t\t(match_operand:SI 1 \"register_operand\")\n \t\t(match_operand:SI 2 \"const_int_operand\")) 0))\n-\t (match_operand:SWI48 3 \"nonimmediate_operand\")))\n+\t (match_operand:SWI48 3 \"register_operand\")))\n (clobber (reg:CC FLAGS_REG))]\n \"(INTVAL (operands[2]) & (GET_MODE_BITSIZE (mode)-1))\n == GET_MODE_BITSIZE (mode)-1\nIndex: testsuite/gcc.target/i386/pr46091-4.c\n===================================================================\n--- testsuite/gcc.target/i386/pr46091-4.c\t(revision 251368)\n+++ testsuite/gcc.target/i386/pr46091-4.c\t(working copy)\n@@ -1,5 +1,6 @@\n /* { dg-do compile } */\n /* { dg-options \"-O2\" } */\n+/* { dg-additional-options \"-mregparm=2\" { target ia32 } } */\n \n int test_1 (int x, int n)\n {\nIndex: testsuite/gcc.target/i386/pr46091-4a.c\n===================================================================\n--- testsuite/gcc.target/i386/pr46091-4a.c\t(revision 251368)\n+++ testsuite/gcc.target/i386/pr46091-4a.c\t(working copy)\n@@ -1,5 +1,6 @@\n /* { dg-do compile } */\n /* { dg-options \"-O2\" } */\n+/* { dg-additional-options \"-mregparm=2\" { target ia32 } } */\n \n int test_1 (int x, int n)\n {\n","prefixes":["i386"]}