{"id":484,"url":"http://patchwork.ozlabs.org/api/1.0/patches/484/?format=json","project":{"id":2,"url":"http://patchwork.ozlabs.org/api/1.0/projects/2/?format=json","name":"Linux PPC development","link_name":"linuxppc-dev","list_id":"linuxppc-dev.lists.ozlabs.org","list_email":"linuxppc-dev@lists.ozlabs.org","web_url":"https://github.com/linuxppc/wiki/wiki","scm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git","webscm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/"},"msgid":"<421706547.03532@bjtu.edu.cn>","date":"2008-09-18T02:57:12","name":"Linuxppc-dev Digest, Vol 49, Issue 89","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":true,"hash":"4a2747900ca8181662daed00c2344f02d24bb0ed","submitter":{"id":246,"url":"http://patchwork.ozlabs.org/api/1.0/people/246/?format=json","name":"limitjiang","email":"03212009@bjtu.edu.cn"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/421706547.03532@bjtu.edu.cn/mbox/","series":[],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/484/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@ozlabs.org"],"Received":["from ozlabs.org (localhost [127.0.0.1])\n\tby ozlabs.org (Postfix) with ESMTP id E1075DE1B6\n\tfor ;\n\tThu, 18 Sep 2008 13:03:31 +1000 (EST)","from bjtu.edu.cn (unknown [218.249.29.195])\n\tby ozlabs.org (Postfix) with SMTP id 57CCDDDF75\n\tfor ; Thu, 18 Sep 2008 13:03:08 +1000 (EST)","(eyou anti_spam gateway 3.0); Thu, 18 Sep 2008 10:55:47 +0800","from 218.249.29.198 by 218.249.29.195 with SMTP;\n\tThu, 18 Sep 2008 10:55:46 +0800"],"X-Greylist":"delayed 340 seconds by postgrey-1.31 at ozlabs;\n\tThu, 18 Sep 2008 13:03:08 EST","X-EYOU-SPAMVALUE":"0","X-EYOU-DEALDRC":"","Message-ID":["<421706547.03532@bjtu.edu.cn>","<200809181057119397391@bjtu.edu.cn>"],"X-EYOUMAIL-SMTPAUTH":"03212009@bjtu.edu.cn","Date":"Thu, 18 Sep 2008 10:57:12 +0800","From":"\"limitjiang\" <03212009@bjtu.edu.cn>","To":"\"linuxppc-dev@ozlabs.org\" ","References":"<421703169.29555@bjtu.edu.cn>","Subject":"Re: Linuxppc-dev Digest, Vol 49, Issue 89","X-mailer":"Foxmail 6, 10, 201, 22 [cn]","Mime-Version":["1.0","1.0"],"X-BeenThere":"linuxppc-dev@ozlabs.org","X-Mailman-Version":"2.1.11","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"multipart/mixed; boundary=\"===============2112014134==\"","Mime-version":["1.0","1.0"],"Sender":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@ozlabs.org","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@ozlabs.org"},"content":"2008-09-18 \r\n\r\n\r\n\r\nlimitjiang \r\n\r\n\r\n\r\n发件人： linuxppc-dev-request@ozlabs.org \r\n发送时间： 2008-09-18 09:55:11 \r\n收件人： linuxppc-dev@ozlabs.org \r\n抄送： \r\n主题： Linuxppc-dev Digest, Vol 49, Issue 89 \r\n \r\nSend Linuxppc-dev mailing list submissions to\r\nlinuxppc-dev@ozlabs.org\r\n\r\nTo subscribe or unsubscribe via the World Wide Web, visit\r\nhttps://ozlabs.org/mailman/listinfo/linuxppc-dev\r\nor, via email, send a message with subject or body 'help' to\r\nlinuxppc-dev-request@ozlabs.org\r\n\r\nYou can reach the person managing the list at\r\nlinuxppc-dev-owner@ozlabs.org\r\n\r\nWhen replying, please edit your Subject line so it is more specific\r\nthan \"Re: Contents of Linuxppc-dev digest...\"\r\n\r\n\r\nToday's Topics:\r\n\r\n 1. [PATCH v7 2/4] powerpc: Fixes for CONFIG_PTE_64BIT for SMP\r\n support (Kumar Gala)\r\n 2. [PATCH v7 3/4] powerpc/fsl-booke: Fixup 64-bit PTE reading\r\n for SMP support (Kumar Gala)\r\n 3. [PATCH v7 4/4] powerpc/mm: Implement _PAGE_SPECIAL &\r\n pte_special() for 32-bit (Kumar Gala)\r\n\r\n\r\n----------------------------------------------------------------------\r\n\r\nMessage: 1\r\nDate: Wed, 17 Sep 2008 18:00:03 -0500\r\nFrom: Kumar Gala \r\nSubject: [PATCH v7 2/4] powerpc: Fixes for CONFIG_PTE_64BIT for SMP\r\nsupport\r\nTo: linuxppc-dev@ozlabs.org\r\nMessage-ID:\r\n<1221692405-19880-2-git-send-email-galak@kernel.crashing.org >\r\n\r\nThere are some minor issues with support 64-bit PTEs on a 32-bit processor\r\nwhen dealing with SMP.\r\n\r\n* We need to order the stores in set_pte_at to make sure the flag word\r\n is set second.\r\n* Change pte_clear to use pte_update so only the flag word is cleared\r\n* Added a check to set_pte_at to clear the pte if it happened to be set.\r\n\r\nSigned-off-by: Kumar Gala \r\n---\r\n\r\nChanged the set_pte_at checking to deal with the case that it's called\r\nwith a pte that has pte_present and clearing it w/proper ordering.\r\n\r\n- k\r\n\r\n arch/powerpc/include/asm/highmem.h | 2 +-\r\n arch/powerpc/include/asm/pgtable-ppc32.h | 28 +++++++++++++++++++++++-----\r\n 2 files changed, 24 insertions(+), 6 deletions(-)\r\n\r\n-- \r\n1.5.5.1\r\n\r\n\r\n\r\n------------------------------\r\n\r\n_______________________________________________\r\nLinuxppc-dev mailing list\r\nLinuxppc-dev@ozlabs.org\r\nhttps://ozlabs.org/mailman/listinfo/linuxppc-dev\r\n\r\nEnd of Linuxppc-dev Digest, Vol 49, Issue 89\r\n********************************************","diff":"diff --git a/arch/powerpc/include/asm/highmem.h b/arch/powerpc/include/asm/highmem.h\r\nindex 5d99b64..91c5895 100644\r\n--- a/arch/powerpc/include/asm/highmem.h\r\n+++ b/arch/powerpc/include/asm/highmem.h\r\n@@ -84,7 +84,7 @@ static inline void *kmap_atomic_prot(struct page *page, enum km_type type, pgpro\r\n #ifdef CONFIG_DEBUG_HIGHMEM\r\n BUG_ON(!pte_none(*(kmap_pte-idx)));\r\n #endif\r\n- set_pte_at(&init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot));\r\n+ __set_pte_at(&init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot));\r\n flush_tlb_page(NULL, vaddr);\r\n\r\n return (void*) vaddr;\r\ndiff --git a/arch/powerpc/include/asm/pgtable-ppc32.h b/arch/powerpc/include/asm/pgtable-ppc32.h\r\nindex 6fe39e3..d1d23b9 100644\r\n--- a/arch/powerpc/include/asm/pgtable-ppc32.h\r\n+++ b/arch/powerpc/include/asm/pgtable-ppc32.h\r\n@@ -517,7 +517,8 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);\r\n\r\n #define pte_none(pte) ((pte_val(pte) & ~_PTE_NONE_MASK) == 0)\r\n #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)\r\n-#define pte_clear(mm,addr,ptep) do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0)\r\n+#define pte_clear(mm, addr, ptep) \\\r\n+ do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)\r\n\r\n #define pmd_none(pmd) (!pmd_val(pmd))\r\n #define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD)\r\n@@ -612,9 +613,6 @@ static inline unsigned long pte_update(pte_t *p,\r\n return old;\r\n }\r\n #else /* CONFIG_PTE_64BIT */\r\n-/* TODO: Change that to only modify the low word and move set_pte_at()\r\n- * out of line\r\n- */\r\n static inline unsigned long long pte_update(pte_t *p,\r\n unsigned long clr,\r\n unsigned long set)\r\n@@ -652,16 +650,36 @@ static inline unsigned long long pte_update(pte_t *p,\r\n * On machines which use an MMU hash table we avoid changing the\r\n * _PAGE_HASHPTE bit.\r\n */\r\n-static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,\r\n+\r\n+static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,\r\n pte_t *ptep, pte_t pte)\r\n {\r\n #if _PAGE_HASHPTE != 0\r\n pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) & ~_PAGE_HASHPTE);\r\n+#elif defined(CONFIG_PTE_64BIT) && defined(CONFIG_SMP)\r\n+ __asm__ __volatile__(\"\\\r\n+ stw%U0%X0 %2,%0\\n\\\r\n+ eieio\\n\\\r\n+ stw%U0%X0 %L2,%1\"\r\n+ : \"=m\" (*ptep), \"=m\" (*((unsigned char *)ptep+4))\r\n+ : \"r\" (pte) : \"memory\");\r\n #else\r\n *ptep = pte;\r\n #endif\r\n }\r\n\r\n+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,\r\n+ pte_t *ptep, pte_t pte)\r\n+{\r\n+#if defined(CONFIG_PTE_64BIT)\r\n+ if (unlikely(pte_present(*ptep))) {\r\n+ pte_clear(mm, addr, ptep);\r\n+ smp_wmb();\r\n+ }\r\n+#endif\r\n+ __set_pte_at(mm, addr, ptep, pte);\r\n+}\r\n+\r\n /*\r\n * 2.6 calls this without flushing the TLB entry; this is wrong\r\n * for our hash-based implementation, we fix that up here.\r\n-- \r\n1.5.5.1\r\n\r\n\r\n\r\n------------------------------\r\n\r\nMessage: 2\r\nDate: Wed, 17 Sep 2008 18:00:04 -0500\r\nFrom: Kumar Gala \r\nSubject: [PATCH v7 3/4] powerpc/fsl-booke: Fixup 64-bit PTE reading\r\nfor SMP support\r\nTo: linuxppc-dev@ozlabs.org\r\nMessage-ID:\r\n<1221692405-19880-3-git-send-email-galak@kernel.crashing.org >\r\n\r\nWe need to create a false data dependency to ensure the loads of\r\nthe pte are done in the right order.\r\n\r\nSigned-off-by: Kumar Gala \r\n---\r\n arch/powerpc/kernel/head_fsl_booke.S | 26 +++++++++++++++++++++-----\r\n 1 files changed, 21 insertions(+), 5 deletions(-)\r\n\r\ndiff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S\r\nindex 3cb52fa..377e0c1 100644\r\n--- a/arch/powerpc/kernel/head_fsl_booke.S\r\n+++ b/arch/powerpc/kernel/head_fsl_booke.S\r\n@@ -579,13 +579,19 @@ interrupt_base:\r\n\r\n FIND_PTE\r\n andc. r13,r13,r11 /* Check permission */\r\n- bne 2f /* Bail if permission mismach */\r\n\r\n #ifdef CONFIG_PTE_64BIT\r\n- lwz r13, 0(r12)\r\n+#ifdef CONFIG_SMP\r\n+ subf r10,r11,r12 /* create false data dep */\r\n+ lwzx r13,r11,r10 /* Get upper pte bits */\r\n+#else\r\n+ lwz r13,0(r12) /* Get upper pte bits */\r\n+#endif\r\n #endif\r\n\r\n- /* Jump to common tlb load */\r\n+ bne 2f /* Bail if permission/valid mismach */\r\n+\r\n+ /* Jump to common tlb load */\r\n b finish_tlb_load\r\n 2:\r\n /* The bailout. Restore registers to pre-exception conditions\r\n@@ -640,10 +646,20 @@ interrupt_base:\r\n\r\n FIND_PTE\r\n andc. r13,r13,r11 /* Check permission */\r\n+\r\n+#ifdef CONFIG_PTE_64BIT\r\n+#ifdef CONFIG_SMP\r\n+ subf r10,r11,r12 /* create false data dep */\r\n+ lwzx r13,r11,r10 /* Get upper pte bits */\r\n+#else\r\n+ lwz r13,0(r12) /* Get upper pte bits */\r\n+#endif\r\n+#endif\r\n+\r\n bne 2f /* Bail if permission mismach */\r\n\r\n #ifdef CONFIG_PTE_64BIT\r\n- lwz r13, 0(r12)\r\n+ lwz r13,0(r12)\r\n #endif\r\n\r\n /* Jump to common TLB load point */\r\n@@ -702,7 +718,7 @@ interrupt_base:\r\n /*\r\n * Both the instruction and data TLB miss get to this\r\n * point to load the TLB.\r\n- * r10 - EA of fault\r\n+ * r10 - available to use\r\n * r11 - TLB (info from Linux PTE)\r\n * r12 - available to use\r\n * r13 - upper bits of PTE (if PTE_64BIT) or available to use\r\n-- \r\n1.5.5.1\r\n\r\n\r\n\r\n------------------------------\r\n\r\nMessage: 3\r\nDate: Wed, 17 Sep 2008 18:00:05 -0500\r\nFrom: Kumar Gala \r\nSubject: [PATCH v7 4/4] powerpc/mm: Implement _PAGE_SPECIAL &\r\npte_special() for 32-bit\r\nTo: linuxppc-dev@ozlabs.org\r\nMessage-ID:\r\n<1221692405-19880-4-git-send-email-galak@kernel.crashing.org >\r\n\r\nImplement _PAGE_SPECIAL and pte_special() for 32-bit powerpc. This bit will\r\nbe used by the fast get_user_pages() to differenciate PTEs that correspond\r\nto a valid struct page from special mappings that don't such as IO mappings\r\nobtained via io_remap_pfn_ranges().\r\n\r\nWe currently only implement this on sub-arch that support SMP or will so\r\nin the future (6xx, 44x, FSL-BookE) and not (8xx, 40x).\r\n\r\nSigned-off-by: Kumar Gala \r\nAcked-by: Benjamin Herrenschmidt \r\n---\r\n arch/powerpc/include/asm/pgtable-ppc32.h | 15 +++++++++++++--\r\n 1 files changed, 13 insertions(+), 2 deletions(-)\r\n\r\ndiff --git a/arch/powerpc/include/asm/pgtable-ppc32.h b/arch/powerpc/include/asm/pgtable-ppc32.h\r\nindex d1d23b9..e8f31a5 100644\r\n--- a/arch/powerpc/include/asm/pgtable-ppc32.h\r\n+++ b/arch/powerpc/include/asm/pgtable-ppc32.h\r\n@@ -261,6 +261,7 @@ extern int icache_44x_need_flush;\r\n #define _PAGE_HWEXEC 0x00000004 /* H: Execute permission */\r\n #define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */\r\n #define _PAGE_DIRTY 0x00000010 /* S: Page dirty */\r\n+#define _PAGE_SPECIAL 0x00000020 /* S: Special page */\r\n #define _PAGE_USER 0x00000040 /* S: User page */\r\n #define _PAGE_ENDIAN 0x00000080 /* H: E bit */\r\n #define _PAGE_GUARDED 0x00000100 /* H: G bit */\r\n@@ -276,6 +277,7 @@ extern int icache_44x_need_flush;\r\n /* ERPN in a PTE never gets cleared, ignore it */\r\n #define _PTE_NONE_MASK 0xffffffff00000000ULL\r\n\r\n+#define __HAVE_ARCH_PTE_SPECIAL\r\n\r\n #elif defined(CONFIG_FSL_BOOKE)\r\n /*\r\n@@ -305,6 +307,7 @@ extern int icache_44x_need_flush;\r\n #define _PAGE_COHERENT 0x00100 /* H: M bit */\r\n #define _PAGE_NO_CACHE 0x00200 /* H: I bit */\r\n #define _PAGE_WRITETHRU 0x00400 /* H: W bit */\r\n+#define _PAGE_SPECIAL 0x00800 /* S: Special page */\r\n\r\n #ifdef CONFIG_PTE_64BIT\r\n /* ERPN in a PTE never gets cleared, ignore it */\r\n@@ -315,6 +318,8 @@ extern int icache_44x_need_flush;\r\n #define _PMD_PRESENT_MASK (PAGE_MASK)\r\n #define _PMD_BAD (~PAGE_MASK)\r\n\r\n+#define __HAVE_ARCH_PTE_SPECIAL\r\n+\r\n #elif defined(CONFIG_8xx)\r\n /* Definitions for 8xx embedded chips. */\r\n #define _PAGE_PRESENT 0x0001 /* Page is valid */\r\n@@ -362,6 +367,7 @@ extern int icache_44x_need_flush;\r\n #define _PAGE_ACCESSED 0x100 /* R: page referenced */\r\n #define _PAGE_EXEC 0x200 /* software: i-cache coherency required */\r\n #define _PAGE_RW 0x400 /* software: user write access allowed */\r\n+#define _PAGE_SPECIAL 0x800 /* software: Special page */\r\n\r\n #define _PTE_NONE_MASK _PAGE_HASHPTE\r\n\r\n@@ -372,6 +378,8 @@ extern int icache_44x_need_flush;\r\n /* Hash table based platforms need atomic updates of the linux PTE */\r\n #define PTE_ATOMIC_UPDATES 1\r\n\r\n+#define __HAVE_ARCH_PTE_SPECIAL\r\n+\r\n #endif\r\n\r\n /*\r\n@@ -404,6 +412,9 @@ extern int icache_44x_need_flush;\r\n #ifndef _PAGE_WRITETHRU\r\n #define _PAGE_WRITETHRU 0\r\n #endif\r\n+#ifndef _PAGE_SPECIAL\r\n+#define _PAGE_SPECIAL 0\r\n+#endif\r\n #ifndef _PMD_PRESENT_MASK\r\n #define _PMD_PRESENT_MASK _PMD_PRESENT\r\n #endif\r\n@@ -534,7 +545,7 @@ static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; }\r\n static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }\r\n static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }\r\n static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }\r\n-static inline int pte_special(pte_t pte) { return 0; }\r\n+static inline int pte_special(pte_t pte) { return pte_val(pte) & _PAGE_SPECIAL; }\r\n\r\n static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; }\r\n static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; }\r\n@@ -553,7 +564,7 @@ static inline pte_t pte_mkdirty(pte_t pte) {\r\n static inline pte_t pte_mkyoung(pte_t pte) {\r\n pte_val(pte) |= _PAGE_ACCESSED; return pte; }\r\n static inline pte_t pte_mkspecial(pte_t pte) {\r\n- return pte; }\r\n+ pte_val(pte) |= _PAGE_SPECIAL; return pte; }\r\n static inline unsigned long pte_pgprot(pte_t pte)\r\n {\r\n return __pgprot(pte_val(pte)) & PAGE_PROT_BITS;\r\n","prefixes":[]}