{"id":2223059,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2223059/?format=json","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/1.0/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260414-upstream_pinctrl-v6-2-709f2127da33@aspeedtech.com>","date":"2026-04-14T09:39:00","name":"[v6,2/3] dt-bindings: mfd: aspeed,ast2x00-scu: Describe AST2700 SCU0","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"294b9c0e37b485975f137b5ed5e794040a26302a","submitter":{"id":80235,"url":"http://patchwork.ozlabs.org/api/1.0/people/80235/?format=json","name":"Billy Tsai","email":"billy_tsai@aspeedtech.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260414-upstream_pinctrl-v6-2-709f2127da33@aspeedtech.com/mbox/","series":[{"id":499805,"url":"http://patchwork.ozlabs.org/api/1.0/series/499805/?format=json","date":"2026-04-14T09:38:58","name":"pinctrl: aspeed: Add AST2700 SoC0 support","version":6,"mbox":"http://patchwork.ozlabs.org/series/499805/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223059/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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arc=none smtp.client-ip=211.20.114.72","From":"Billy Tsai ","Date":"Tue, 14 Apr 2026 17:39:00 +0800","Subject":"[PATCH v6 2/3] dt-bindings: mfd: aspeed,ast2x00-scu: Describe\n AST2700 SCU0","Precedence":"bulk","X-Mailing-List":"linux-gpio@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-ID":"<20260414-upstream_pinctrl-v6-2-709f2127da33@aspeedtech.com>","References":"<20260414-upstream_pinctrl-v6-0-709f2127da33@aspeedtech.com>","In-Reply-To":"<20260414-upstream_pinctrl-v6-0-709f2127da33@aspeedtech.com>","To":"Lee Jones , Rob Herring , \"Krzysztof\n Kozlowski\" , Conor Dooley , \"Joel\n Stanley\" , Andrew Jeffery ,\n\t\"Linus Walleij\" , Billy Tsai ,\n\t\"Bartosz Golaszewski\" , Ryan Chen ","CC":"Andrew Jeffery , ,\n\t, ,\n\t, ,\n\t, ","X-Mailer":"b4 0.14.3","X-Developer-Signature":"v=1; a=ed25519-sha256; t=1776159555; l=5282;\n i=billy_tsai@aspeedtech.com; s=20251118; h=from:subject:message-id;\n bh=1adOzN89BJlq56ikXHBSEpPPcUIuo6AxNQzlti780x8=;\n b=lUxsJPh0Uh7M+PWU69Q6zBK9UxsmwYd4K1lc21YcI0lMbJ4NkQEgtwxkFdHUSNqAGs5WfsgrS\n cSLI5mQe7UKDgA0/J7hhHmfYWatKrdD5vEoGuNo2FRqVHBV0VH/Bgfb","X-Developer-Key":"i=billy_tsai@aspeedtech.com; a=ed25519;\n pk=/A8qvgZ6CPfnwKgT6/+k+nvXOkN477MshEGJvVdzeeQ="},"content":"AST2700 consists of two interconnected SoC instances, each with its own\nSystem Control Unit (SCU). The SCU0 provides pin control, interrupt\ncontrollers, clocks, resets, and address-space mappings for the\nSecondary and Tertiary Service Processors (SSP and TSP).\n\nDescribe the SSP/TSP address mappings using the standard\nmemory-region and memory-region-names properties.\n\nDisallow legacy child nodes that are not present on AST2700, including\np2a-control and smp-memram. The latter is unnecessary as software can\naccess the scratch registers via the SCU syscon.\n\nAlso allow the AST2700 SoC0 pin controller to be described as a child\nnode of the SCU0, and add an example illustrating the SCU0 layout,\nincluding reserved-memory, interrupt controllers, and pinctrl.\n\nSigned-off-by: Billy Tsai \n---\n .../bindings/mfd/aspeed,ast2x00-scu.yaml | 112 +++++++++++++++++++++\n 1 file changed, 112 insertions(+)","diff":"diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml\nindex a87f31fce019..d65897576a40 100644\n--- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml\n+++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml\n@@ -46,6 +46,17 @@ properties:\n '#reset-cells':\n const: 1\n \n+ memory-region:\n+ items:\n+ - description: Region mapped through the first SSP address window.\n+ - description: Region mapped through the second SSP address window.\n+ - description: Region mapped through the TSP address window.\n+ memory-region-names:\n+ items:\n+ - const: ssp-0\n+ - const: ssp-1\n+ - const: tsp\n+\n patternProperties:\n '^p2a-control@[0-9a-f]+$':\n description: >\n@@ -87,6 +98,7 @@ patternProperties:\n - aspeed,ast2400-pinctrl\n - aspeed,ast2500-pinctrl\n - aspeed,ast2600-pinctrl\n+ - aspeed,ast2700-soc0-pinctrl\n \n required:\n - compatible\n@@ -156,6 +168,29 @@ required:\n - '#clock-cells'\n - '#reset-cells'\n \n+allOf:\n+ - if:\n+ properties:\n+ compatible:\n+ contains:\n+ anyOf:\n+ - const: aspeed,ast2700-scu0\n+ - const: aspeed,ast2700-scu1\n+ then:\n+ patternProperties:\n+ '^p2a-control@[0-9a-f]+$': false\n+ '^smp-memram@[0-9a-f]+$': false\n+\n+ - if:\n+ properties:\n+ compatible:\n+ contains:\n+ const: aspeed,ast2700-scu0\n+ else:\n+ properties:\n+ memory-region: false\n+ memory-region-names: false\n+\n additionalProperties: false\n \n examples:\n@@ -180,4 +215,81 @@ examples:\n reg = <0x7c 0x4>, <0x150 0x8>;\n };\n };\n+\n+ - |\n+ / {\n+ #address-cells = <2>;\n+ #size-cells = <2>;\n+\n+ reserved-memory {\n+ #address-cells = <2>;\n+ #size-cells = <2>;\n+ ranges;\n+\n+ ssp_region_0: memory@400000000 {\n+ reg = <0x4 0x00000000 0x0 0x01000000>;\n+ no-map;\n+ };\n+\n+ ssp_region_1: memory@401000000 {\n+ reg = <0x4 0x01000000 0x0 0x01000000>;\n+ no-map;\n+ };\n+\n+ tsp_region: memory@402000000 {\n+ reg = <0x4 0x02000000 0x0 0x01000000>;\n+ no-map;\n+ };\n+ };\n+\n+ bus {\n+ #address-cells = <2>;\n+ #size-cells = <2>;\n+\n+ syscon@12c02000 {\n+ compatible = \"aspeed,ast2700-scu0\", \"syscon\", \"simple-mfd\";\n+ reg = <0 0x12c02000 0 0x1000>;\n+ ranges = <0x0 0x0 0x12c02000 0x1000>;\n+ #address-cells = <1>;\n+ #size-cells = <1>;\n+ #clock-cells = <1>;\n+ #reset-cells = <1>;\n+\n+ memory-region = <&ssp_region_0>, <&ssp_region_1>,\n+ <&tsp_region>;\n+ memory-region-names = \"ssp-0\", \"ssp-1\", \"tsp\";\n+\n+ silicon-id@0 {\n+ compatible = \"aspeed,ast2700-silicon-id\", \"aspeed,silicon-id\";\n+ reg = <0x0 0x4>;\n+ };\n+\n+ interrupt-controller@1b0 {\n+ compatible = \"aspeed,ast2700-scu-ic0\";\n+ reg = <0x1b0 0x4>;\n+ #interrupt-cells = <1>;\n+ interrupts-extended = <&intc0 97>;\n+ interrupt-controller;\n+ };\n+\n+ interrupt-controller@1e0 {\n+ compatible = \"aspeed,ast2700-scu-ic1\";\n+ reg = <0x1e0 0x4>;\n+ #interrupt-cells = <1>;\n+ interrupts-extended = <&intc0 98>;\n+ interrupt-controller;\n+ };\n+\n+ pinctrl@400 {\n+ compatible = \"aspeed,ast2700-soc0-pinctrl\";\n+ reg = <0x400 0x318>;\n+ emmc-state {\n+ function = \"EMMC\";\n+ groups = \"EMMCG1\";\n+ };\n+ };\n+ };\n+ };\n+ };\n+\n ...\n","prefixes":["v6","2/3"]}