{"id":2221267,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2221267/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260409035015.132370-3-richard.henderson@linaro.org>","date":"2026-04-09T03:50:10","name":"[v2,2/7] target/arm: Only define aarch64_untagged_addr for aarch64","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"632d96f62a8aef5d1f7ff14c64f29f8f5cf2e616","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.0/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260409035015.132370-3-richard.henderson@linaro.org/mbox/","series":[{"id":499232,"url":"http://patchwork.ozlabs.org/api/1.0/series/499232/?format=json","date":"2026-04-09T03:50:08","name":"target/arm: Remove bswap_code","version":2,"mbox":"http://patchwork.ozlabs.org/series/499232/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221267/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=X07824hQ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4frmFB2RwFz1yD3\n\tfor ; Thu, 09 Apr 2026 13:51:10 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wAgPY-0000dU-O8; Wed, 08 Apr 2026 23:50:32 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wAgPY-0000dK-3T\n for qemu-devel@nongnu.org; Wed, 08 Apr 2026 23:50:32 -0400","from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wAgPW-0003sK-I1\n for qemu-devel@nongnu.org; Wed, 08 Apr 2026 23:50:31 -0400","by mail-pg1-x52f.google.com with SMTP id\n 41be03b00d2f7-c76cce85bd9so178247a12.1\n for ; Wed, 08 Apr 2026 20:50:30 -0700 (PDT)","from stoup.. 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helo=mail-pg1-x52f.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Signed-off-by: Richard Henderson \n---\n target/arm/cpu.c | 28 +++++++++++++++-------------\n 1 file changed, 15 insertions(+), 13 deletions(-)","diff":"diff --git a/target/arm/cpu.c b/target/arm/cpu.c\nindex b62de8addf..35b661904f 100644\n--- a/target/arm/cpu.c\n+++ b/target/arm/cpu.c\n@@ -2262,7 +2262,19 @@ static const char *arm_gdb_get_core_xml_file(CPUState *cs)\n return \"arm-core.xml\";\n }\n \n-#ifdef CONFIG_USER_ONLY\n+#ifndef CONFIG_USER_ONLY\n+#include \"hw/core/sysemu-cpu-ops.h\"\n+\n+static const struct SysemuCPUOps arm_sysemu_ops = {\n+ .has_work = arm_cpu_has_work,\n+ .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug,\n+ .asidx_from_attrs = arm_asidx_from_attrs,\n+ .write_elf32_note = arm_cpu_write_elf32_note,\n+ .write_elf64_note = arm_cpu_write_elf64_note,\n+ .internal_is_big_endian = arm_cpu_internal_is_big_endian,\n+ .legacy_vmsd = &vmstate_arm_cpu,\n+};\n+#elif defined(TARGET_AARCH64)\n /**\n * aarch64_untagged_addr:\n *\n@@ -2286,18 +2298,6 @@ static vaddr aarch64_untagged_addr(CPUState *cs, vaddr x)\n }\n return x;\n }\n-#else\n-#include \"hw/core/sysemu-cpu-ops.h\"\n-\n-static const struct SysemuCPUOps arm_sysemu_ops = {\n- .has_work = arm_cpu_has_work,\n- .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug,\n- .asidx_from_attrs = arm_asidx_from_attrs,\n- .write_elf32_note = arm_cpu_write_elf32_note,\n- .write_elf64_note = arm_cpu_write_elf64_note,\n- .internal_is_big_endian = arm_cpu_internal_is_big_endian,\n- .legacy_vmsd = &vmstate_arm_cpu,\n-};\n #endif\n \n #ifdef CONFIG_TCG\n@@ -2340,7 +2340,9 @@ static const TCGCPUOps arm_tcg_ops = {\n #ifdef CONFIG_USER_ONLY\n .record_sigsegv = arm_cpu_record_sigsegv,\n .record_sigbus = arm_cpu_record_sigbus,\n+# ifdef TARGET_AARCH64\n .untagged_addr = aarch64_untagged_addr,\n+# endif\n #else\n .tlb_fill_align = arm_cpu_tlb_fill_align,\n .pointer_wrap = aprofile_pointer_wrap,\n","prefixes":["v2","2/7"]}