{"id":2221204,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2221204/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<177564643888.23414.7922925369077631439-4@git.sr.ht>","date":"2026-04-07T13:38:47","name":"[qemu,v2,4/7] ot_uart: replace individual IRQ fields with array, add missing IRQs","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"7ce3402ac008677689fb8b441d19500dc518c172","submitter":{"id":92675,"url":"http://patchwork.ozlabs.org/api/1.0/people/92675/?format=json","name":"~lexbaileylowrisc","email":"lexbaileylowrisc@git.sr.ht"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/177564643888.23414.7922925369077631439-4@git.sr.ht/mbox/","series":[{"id":499197,"url":"http://patchwork.ozlabs.org/api/1.0/series/499197/?format=json","date":"2026-04-07T14:11:43","name":"Update opentitan uart (part of supporting opentitan version 1)","version":2,"mbox":"http://patchwork.ozlabs.org/series/499197/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221204/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=fail reason=\"key not found in DNS\" header.d=git.sr.ht\n header.i=@git.sr.ht header.a=rsa-sha256 header.s=20240113 header.b=mjm+bSDI;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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bh=I2vJF8Ao5uoGzmkiFFS4anH8vSW24HuJ9ZbFaJQD0us=;\n c=simple/simple; d=git.sr.ht;\n h=From:Date:Subject:Reply-to:In-Reply-To:To:Cc; q=dns/txt; s=20240113;\n t=1775646440; v=1;\n b=mjm+bSDIhe9pAR8EbLd96UGMmRKB1LNHJkwh8mDXpvAkBZkwz1LGbuh3mYHHiR2w69T+48fv\n io05KU1HzZnFbtZ7MlFwraxVBxX1z6/nvqFXkaYJE/iAvTEqFMPx+Jl0Pp2GuQ+DEN9MBROs0Fa\n 2RBIkhEzl04ZeP2vXUDaUwQ+EOuK9941dPcL09AJs2dqMrrQq4z5J9AwxAU2ic8rmPzoI84A0hm\n CNp/KHPerSXvMG5tgnmHe5qsPQXLp7OimHcDi+p7cgpSbOCPknO8QSjUuW3baConSQlhM2rlC72\n aGU2HpXil27ZqX9LTwos/2x/RVIuKY82w1bnzE+zvyxWg==","From":"~lexbaileylowrisc ","Date":"Tue, 07 Apr 2026 14:38:47 +0100","Subject":"[PATCH qemu v2 4/7] ot_uart: replace individual IRQ fields with\n array, add missing IRQs","Message-ID":"<177564643888.23414.7922925369077631439-4@git.sr.ht>","X-Mailer":"git.sr.ht","In-Reply-To":"<177564643888.23414.7922925369077631439-0@git.sr.ht>","To":"qemu-riscv@nongnu.org, Alistair Francis ","Cc":"Paolo Bonzini ,\n =?utf-8?q?Marc-Andr=C3=A9?= Lureau ,\n Palmer Dabbelt , Weiwei Li ,\n Daniel Henrique Barboza ,\n Liu Zhiwei ,\n Chao Liu , qemu-devel@nongnu.org,\n Amit Kumar-Hermosillo , nabihestefan@google.com","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"quoted-printable","MIME-Version":"1.0","Received-SPF":"pass client-ip=46.23.81.152; envelope-from=outgoing@sr.ht;\n helo=mail-a.sr.ht","X-Spam_score_int":"-5","X-Spam_score":"-0.6","X-Spam_bar":"/","X-Spam_report":"(-0.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_12_24=1.049,\n DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Reply-To":"~lexbaileylowrisc ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Lex Bailey \n\nThere are 9 interrupts in the OpenTitan UART device.\nThese are documented here:\nhttps://opentitan.org/book/hw/ip/uart/doc/theory_of_operation.html#interrupts\n\nThis commit removes the individually named interrupts (of which there was only four)\nand replaces them with an array of 9 interrupts.\n\nSigned-off-by: Lex Bailey \n---\n hw/char/ot_uart.c | 44 +++++++++++++--------------------------\n include/hw/char/ot_uart.h | 5 +----\n 2 files changed, 15 insertions(+), 34 deletions(-)","diff":"diff --git a/hw/char/ot_uart.c b/hw/char/ot_uart.c\nindex 3bf3295b1b..923aab12af 100644\n--- a/hw/char/ot_uart.c\n+++ b/hw/char/ot_uart.c\n@@ -107,6 +107,7 @@ REG32(TIMEOUT_CTRL, 0x30)\n #define OT_UART_NCO_BITS 16\n #define OT_UART_TX_FIFO_SIZE 128\n #define OT_UART_RX_FIFO_SIZE 128\n+#define OT_UART_IRQ_NUM 9\n \n #define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))\n \n@@ -116,31 +117,11 @@ REG32(TIMEOUT_CTRL, 0x30)\n \n static void ot_uart_update_irqs(OtUARTState *s)\n {\n- if (s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE]\n- & INTR_TX_WATERMARK_MASK) {\n- qemu_set_irq(s->tx_watermark, 1);\n- } else {\n- qemu_set_irq(s->tx_watermark, 0);\n- }\n-\n- if (s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE]\n- & INTR_RX_WATERMARK_MASK) {\n- qemu_set_irq(s->rx_watermark, 1);\n- } else {\n- qemu_set_irq(s->rx_watermark, 0);\n- }\n+ uint32_t state_masked = s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE];\n \n- if (s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE] & INTR_TX_EMPTY_MASK) {\n- qemu_set_irq(s->tx_empty, 1);\n- } else {\n- qemu_set_irq(s->tx_empty, 0);\n- }\n-\n- if (s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE]\n- & INTR_RX_OVERFLOW_MASK) {\n- qemu_set_irq(s->rx_overflow, 1);\n- } else {\n- qemu_set_irq(s->rx_overflow, 0);\n+ for (int index = 0; index < OT_UART_IRQ_NUM; index++) {\n+ bool level = (state_masked & (1U << index)) != 0;\n+ qemu_set_irq(s->irqs[index], level);\n }\n }\n \n@@ -291,6 +272,9 @@ static void ot_uart_reset_enter(Object *obj, ResetType type)\n s->regs[R_STATUS] = 0x0000003c;\n \n s->tx_watermark_level = 0;\n+ for (unsigned index = 0; index < ARRAY_SIZE(s->irqs); index++) {\n+ qemu_set_irq(s->irqs[index], 0);\n+ }\n ot_uart_reset_tx_fifo(s);\n ot_uart_reset_rx_fifo(s);\n \n@@ -562,21 +546,21 @@ static void ot_uart_init(Object *obj)\n ot_uart_clk_update, s, ClockUpdate);\n clock_set_hz(s->f_clk, OT_UART_CLOCK);\n \n- sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_watermark);\n- sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->rx_watermark);\n- sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_empty);\n- sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->rx_overflow);\n+ for (unsigned index = 0; index < OT_UART_IRQ_NUM; index++) {\n+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irqs[index]);\n+ }\n \n memory_region_init_io(&s->mmio, obj, &ot_uart_ops, s,\n TYPE_OT_UART, 0x400);\n sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);\n \n /*\n- * This array has a fixed size in the header. This assertion is used to\n- * check that it is consistent with the definition in this file. This is\n+ * These arrays have fixed sizes in the header. These assertions are used to\n+ * check that they are consistent with the definitions in this file. This is\n * ostensibly a runtime check, but may be optimised away by the compiler.\n */\n assert(REGS_SIZE == sizeof(s->regs));\n+ assert(OT_UART_IRQ_NUM * sizeof(qemu_irq) == sizeof(s->irqs));\n }\n \n static void ot_uart_realize(DeviceState *dev, Error **errp)\ndiff --git a/include/hw/char/ot_uart.h b/include/hw/char/ot_uart.h\nindex f489612700..a2c5ff8b33 100644\n--- a/include/hw/char/ot_uart.h\n+++ b/include/hw/char/ot_uart.h\n@@ -42,6 +42,7 @@ struct OtUARTState {\n \n /* */\n MemoryRegion mmio;\n+ qemu_irq irqs[9];\n \n uint32_t tx_level;\n \n@@ -59,10 +60,6 @@ struct OtUARTState {\n Clock *f_clk;\n \n CharFrontend chr;\n- qemu_irq tx_watermark;\n- qemu_irq rx_watermark;\n- qemu_irq tx_empty;\n- qemu_irq rx_overflow;\n };\n \n struct OtUARTClass {\n","prefixes":["qemu","v2","4/7"]}