{"id":2221187,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2221187/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260408041953.1899532-17-brian.cain@oss.qualcomm.com>","date":"2026-04-08T04:19:41","name":"[v4,16/28] target/hexagon: Add sysemu_ops, cpu_get_phys_page_debug()","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"be00265894cbbf60efe60593a9cd50fee0565b95","submitter":{"id":89839,"url":"http://patchwork.ozlabs.org/api/1.0/people/89839/?format=json","name":"Brian Cain","email":"brian.cain@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260408041953.1899532-17-brian.cain@oss.qualcomm.com/mbox/","series":[{"id":499179,"url":"http://patchwork.ozlabs.org/api/1.0/series/499179/?format=json","date":"2026-04-08T04:19:31","name":"Hexagon system emulation - Part 2/3","version":4,"mbox":"http://patchwork.ozlabs.org/series/499179/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221187/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=l87NV24K;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=ZCtlaK5t;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mx0b-0031df01.pphosted.com","X-Spam_score_int":"-27","X-Spam_score":"-2.8","X-Spam_bar":"--","X-Spam_report":"(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Brian Cain \n\nReviewed-by: Taylor Simpson \nSigned-off-by: Brian Cain \n---\n target/hexagon/cpu.c | 32 ++++++++++++++++++++++++++++++++\n 1 file changed, 32 insertions(+)","diff":"diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c\nindex 098a3918c94..d130a02f5d5 100644\n--- a/target/hexagon/cpu.c\n+++ b/target/hexagon/cpu.c\n@@ -20,6 +20,7 @@\n #include \"qemu/qemu-print.h\"\n #include \"cpu.h\"\n #include \"internal.h\"\n+#include \"exec/cputlb.h\"\n #include \"exec/translation-block.h\"\n #include \"qapi/error.h\"\n #include \"hw/core/qdev-properties.h\"\n@@ -37,6 +38,7 @@\n #include \"accel/tcg/cpu-ldst.h\"\n #include \"qemu/main-loop.h\"\n #include \"hex_interrupts.h\"\n+#include \"hexswi.h\"\n #include \"exec/cpu-interrupt.h\"\n #include \"exec/target_page.h\"\n #include \"hw/hexagon/hexagon_globalreg.h\"\n@@ -499,6 +501,24 @@ static void find_qemu_subpage(vaddr *addr, hwaddr *phys, uint64_t page_size)\n *phys += offset;\n }\n \n+static hwaddr hexagon_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)\n+{\n+ CPUHexagonState *env = cpu_env(cs);\n+ hwaddr phys_addr;\n+ int prot;\n+ uint64_t page_size = 0;\n+ int32_t excp = 0;\n+ int mmu_idx = MMU_KERNEL_IDX;\n+\n+ if (get_physical_address(env, &phys_addr, &prot, &page_size, &excp,\n+ addr, 0, mmu_idx)) {\n+ find_qemu_subpage(&addr, &phys_addr, page_size);\n+ return phys_addr;\n+ }\n+\n+ return -1;\n+}\n+\n \n #define INVALID_BADVA 0xbadabada\n \n@@ -606,6 +626,13 @@ static bool hexagon_tlb_fill(CPUState *cs, vaddr address, int size,\n do_raise_exception(env, cs->exception_index, env->gpr[HEX_REG_PC], retaddr);\n }\n \n+#include \"hw/core/sysemu-cpu-ops.h\"\n+\n+static const struct SysemuCPUOps hexagon_sysemu_ops = {\n+ .has_work = hexagon_cpu_has_work,\n+ .get_phys_page_debug = hexagon_cpu_get_phys_page_debug,\n+};\n+\n static bool hexagon_cpu_exec_interrupt(CPUState *cs, int interrupt_request)\n {\n CPUHexagonState *env = cpu_env(cs);\n@@ -648,6 +675,8 @@ static const TCGCPUOps hexagon_tcg_ops = {\n .pointer_wrap = hexagon_pointer_wrap,\n .cpu_exec_reset = cpu_reset,\n .tlb_fill = hexagon_tlb_fill,\n+ .cpu_exec_halt = hexagon_cpu_has_work,\n+ .do_interrupt = hexagon_cpu_do_interrupt,\n #endif /* !CONFIG_USER_ONLY */\n };\n \n@@ -675,9 +704,12 @@ static void hexagon_cpu_class_init(ObjectClass *c, const void *data)\n cc->gdb_core_xml_file = \"hexagon-core.xml\";\n cc->disas_set_info = hexagon_cpu_disas_set_info;\n #ifndef CONFIG_USER_ONLY\n+ cc->sysemu_ops = &hexagon_sysemu_ops;\n dc->vmsd = &vmstate_hexagon_cpu;\n #endif\n+#ifdef CONFIG_TCG\n cc->tcg_ops = &hexagon_tcg_ops;\n+#endif\n }\n \n #define DEFINE_CPU(type_name, initfn) \\\n","prefixes":["v4","16/28"]}