{"id":2221167,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2221167/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<177564643888.23414.7922925369077631439-7@git.sr.ht>","date":"2026-04-07T14:03:54","name":"[qemu,v2,7/7] ot_uart: add tracing","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"85cd14bc0f11e94e980da5da001015360185df2d","submitter":{"id":92675,"url":"http://patchwork.ozlabs.org/api/1.0/people/92675/?format=json","name":"~lexbaileylowrisc","email":"lexbaileylowrisc@git.sr.ht"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/177564643888.23414.7922925369077631439-7@git.sr.ht/mbox/","series":[{"id":499197,"url":"http://patchwork.ozlabs.org/api/1.0/series/499197/?format=json","date":"2026-04-07T14:11:43","name":"Update opentitan uart (part of supporting opentitan version 1)","version":2,"mbox":"http://patchwork.ozlabs.org/series/499197/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221167/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=fail reason=\"key not found in DNS\" header.d=git.sr.ht\n header.i=@git.sr.ht header.a=rsa-sha256 header.s=20240113 header.b=a/Orkh+e;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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bh=1/4coCVA2N6x/mToKvWs3wRYdqXcBrzAmfmEEcyd3Os=;\n c=simple/simple; d=git.sr.ht;\n h=From:Date:Subject:Reply-to:In-Reply-To:To:Cc; q=dns/txt; s=20240113;\n t=1775646441; v=1;\n b=a/Orkh+eyzLWobqbjsDavq6tCl1jxgNjS25D67QCb66p3VBImMEe1fM7orVAZuKAEYctHeXU\n 4aWUwgstdxks2Dagdo1wTtmadkx4pBpl5HUP5Rfl1uh6SIkW9JRQpyGDM73fzYX2oyj7tWFfaHa\n ZSMK83GTZvXnM6ZkXL66wx7yLV3Dxpb9B6T8JN+aYqKC84191yj2cNvaeo0z6BEdAQq16y9QW0F\n PN6ERT1p8b4cIp6lX/rGL3jncsprpgq6PtEsEwWqC44TOFaIrf8EBRYBRTG8zMUJ2cyZqABqH6N\n fsfjKP4Ibow4CJVLngOfXqEzMiB/koZX592+ZTTzBW4ww==","From":"~lexbaileylowrisc ","Date":"Tue, 07 Apr 2026 15:03:54 +0100","Subject":"[PATCH qemu v2 7/7] ot_uart: add tracing","Message-ID":"<177564643888.23414.7922925369077631439-7@git.sr.ht>","X-Mailer":"git.sr.ht","In-Reply-To":"<177564643888.23414.7922925369077631439-0@git.sr.ht>","To":"qemu-riscv@nongnu.org, Alistair Francis ","Cc":"Paolo Bonzini ,\n =?utf-8?q?Marc-Andr=C3=A9?= Lureau ,\n Palmer Dabbelt , Weiwei Li ,\n Daniel Henrique Barboza ,\n Liu Zhiwei ,\n Chao Liu , qemu-devel@nongnu.org,\n Amit Kumar-Hermosillo , nabihestefan@google.com","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"quoted-printable","MIME-Version":"1.0","Received-SPF":"pass client-ip=46.23.81.152; envelope-from=outgoing@sr.ht;\n helo=mail-a.sr.ht","X-Spam_score_int":"-5","X-Spam_score":"-0.6","X-Spam_bar":"/","X-Spam_report":"(-0.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_12_24=1.049,\n DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Reply-To":"~lexbaileylowrisc ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Lex Bailey \n\nAdded some tracing to the OpenTitan UART for transparency when debugging\n\nSigned-off-by: Lex Bailey \n---\n hw/char/ot_uart.c | 30 ++++++++++++++++++++++++++++++\n hw/char/trace-events | 8 ++++++++\n hw/riscv/opentitan.c | 1 +\n include/hw/char/ot_uart.h | 1 +\n 4 files changed, 40 insertions(+)","diff":"diff --git a/hw/char/ot_uart.c b/hw/char/ot_uart.c\nindex 1dda771724..6f7b8946e8 100644\n--- a/hw/char/ot_uart.c\n+++ b/hw/char/ot_uart.c\n@@ -30,6 +30,7 @@\n #include \"migration/vmstate.h\"\n #include \"qemu/log.h\"\n #include \"qemu/module.h\"\n+#include \"trace.h\"\n \n /* clang-format off */\n REG32(INTR_STATE, 0x00)\n@@ -135,6 +136,9 @@ static void ot_uart_update_irqs(OtUARTState *s)\n {\n uint32_t state_masked = s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE];\n \n+ trace_ot_uart_irqs(s->ot_id, s->regs[R_INTR_STATE], s->regs[R_INTR_ENABLE],\n+ state_masked);\n+\n for (int index = 0; index < OT_UART_IRQ_NUM; index++) {\n bool level = (state_masked & (1U << index)) != 0;\n qemu_set_irq(s->irqs[index], level);\n@@ -156,6 +160,18 @@ static bool ot_uart_is_rx_enabled(const OtUARTState *s)\n return FIELD_EX32(s->regs[R_CTRL], CTRL, RX);\n }\n \n+static void ot_uart_check_baudrate(const OtUARTState *s)\n+{\n+ uint32_t nco = FIELD_EX32(s->regs[R_CTRL], CTRL, NCO);\n+\n+ unsigned baudrate = (unsigned)(((uint64_t)nco * (uint64_t)s->pclk) >>\n+ (R_CTRL_NCO_LENGTH + 4));\n+\n+ if (baudrate) {\n+ trace_ot_uart_check_baudrate(s->ot_id, s->pclk, baudrate);\n+ }\n+}\n+\n static int ot_uart_can_receive(void *opaque)\n {\n OtUARTState *s = opaque;\n@@ -403,6 +419,7 @@ static void ot_uart_clock_input(void *opaque, int irq, int level)\n s->pclk = (unsigned)level;\n \n /* TODO: disable UART transfer when PCLK is 0 */\n+ ot_uart_check_baudrate(s);\n }\n \n static uint64_t ot_uart_read(void *opaque, hwaddr addr, unsigned int size)\n@@ -500,6 +517,10 @@ static uint64_t ot_uart_read(void *opaque, hwaddr addr, unsigned int size)\n break;\n }\n \n+ uint32_t pc = current_cpu->cc->get_pc(current_cpu);\n+ trace_ot_uart_io_read_out(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32,\n+ pc);\n+\n return (uint64_t)val32;\n }\n \n@@ -511,6 +532,9 @@ static void ot_uart_write(void *opaque, hwaddr addr, uint64_t val64,\n \n hwaddr reg = R32_OFF(addr);\n \n+ uint32_t pc = current_cpu->cc->get_pc(current_cpu);\n+ trace_ot_uart_io_write(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32, pc);\n+\n switch (reg) {\n case R_INTR_STATE:\n val32 &= INTR_MASK;\n@@ -541,6 +565,9 @@ static void ot_uart_write(void *opaque, hwaddr addr, uint64_t val64,\n uint32_t prev = s->regs[R_CTRL];\n s->regs[R_CTRL] = val32 & CTRL_MASK;\n uint32_t change = prev ^ s->regs[R_CTRL];\n+ if (change & R_CTRL_NCO_MASK) {\n+ ot_uart_check_baudrate(s);\n+ }\n if ((change & R_CTRL_RX_MASK) && ot_uart_is_rx_enabled(s) &&\n !ot_uart_is_sys_loopack_enabled(s)) {\n qemu_chr_fe_accept_input(&s->chr);\n@@ -621,6 +648,7 @@ static const VMStateDescription vmstate_ot_uart = {\n };\n \n static const Property ot_uart_properties[] = {\n+ DEFINE_PROP_STRING(\"ot-id\", OtUARTState, ot_id),\n DEFINE_PROP_CHR(\"chardev\", OtUARTState, chr),\n DEFINE_PROP_BOOL(\"oversample-break\", OtUARTState, oversample_break, false),\n DEFINE_PROP_BOOL(\"toggle-break\", OtUARTState, toggle_break, false),\n@@ -669,6 +697,8 @@ static void ot_uart_realize(DeviceState *dev, Error **errp)\n {\n OtUARTState *s = OT_UART(dev);\n \n+ g_assert(s->ot_id);\n+\n qdev_init_gpio_in_named(DEVICE(s), &ot_uart_clock_input, \"clock-in\", 1);\n \n fifo8_create(&s->tx_fifo, OT_UART_TX_FIFO_SIZE);\ndiff --git a/hw/char/trace-events b/hw/char/trace-events\nindex a3fcc77287..c859d8af4e 100644\n--- a/hw/char/trace-events\n+++ b/hw/char/trace-events\n@@ -141,3 +141,11 @@ stm32f2xx_usart_receive(char *id, uint8_t chr) \" %s receiving '%c'\"\n # riscv_htif.c\n htif_uart_write_to_host(uint8_t device, uint8_t cmd, uint64_t payload) \"device: %u cmd: %02u payload: %016\" PRIx64\n htif_uart_unknown_device_command(uint8_t device, uint8_t cmd, uint64_t payload) \"device: %u cmd: %02u payload: %016\" PRIx64\n+\n+# ot_uart.c\n+ot_uart_check_baudrate(const char *id, unsigned pclk, unsigned baud) \"%s: @ %u Hz: %u bps\"\n+ot_uart_connect_input_clock(const char *id, const char * srcname) \"%s: %s\"\n+ot_uart_debug(const char *id, const char *msg) \"%s: %s\"\n+ot_uart_io_read_out(const char *id, uint32_t addr, const char *regname, uint32_t val, uint32_t pc) \"%s: addr=0x%02x (%s), val=0x%x, pc=0x%x\"\n+ot_uart_io_write(const char *id, uint32_t addr, const char *regname, uint32_t val, uint32_t pc) \"%s: addr=0x%02x (%s), val=0x%x, pc=0x%x\"\n+ot_uart_irqs(const char *id, uint32_t active, uint32_t mask, uint32_t eff) \"%s: act:0x%08x msk:0x%08x eff:0x%08x\"\ndiff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c\nindex 97c33d1b53..163d3ac3d3 100644\n--- a/hw/riscv/opentitan.c\n+++ b/hw/riscv/opentitan.c\n@@ -133,6 +133,7 @@ static void lowrisc_ibex_soc_init(Object *obj)\n object_initialize_child(obj, \"plic\", &s->plic, TYPE_SIFIVE_PLIC);\n \n object_initialize_child(obj, \"uart\", &s->uart, TYPE_OT_UART);\n+ object_property_set_str(OBJECT(&s->uart), \"ot-id\", \"uart0\", &error_fatal);\n \n object_initialize_child(obj, \"timer\", &s->timer, TYPE_IBEX_TIMER);\n \ndiff --git a/include/hw/char/ot_uart.h b/include/hw/char/ot_uart.h\nindex 221c581e52..7c2b5f3457 100644\n--- a/include/hw/char/ot_uart.h\n+++ b/include/hw/char/ot_uart.h\n@@ -46,6 +46,7 @@ struct OtUARTState {\n unsigned pclk; /* Current input clock */\n const char *clock_src_name; /* IRQ name once connected */\n \n+ char *ot_id;\n DeviceState *clock_src;\n CharFrontend chr;\n bool oversample_break; /* Should mock break in the oversampled VAL reg? */\n","prefixes":["qemu","v2","7/7"]}