{"id":2221127,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2221127/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"","date":"2026-04-08T16:36:55","name":"[v3,04/16] hexagon: group cpu configurations in their own struct","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"26ea5c655d2a38ecce9ddea56cc0a310ee537ac3","submitter":{"id":90606,"url":"http://patchwork.ozlabs.org/api/1.0/people/90606/?format=json","name":"Matheus Tavares Bernardino","email":"matheus.bernardino@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/d7cc954b233ff2a1d7424eb48338473556bac78c.1775665981.git.matheus.bernardino@oss.qualcomm.com/mbox/","series":[{"id":499185,"url":"http://patchwork.ozlabs.org/api/1.0/series/499185/?format=json","date":"2026-04-08T16:36:53","name":"hexagon: add missing HVX float instructions","version":3,"mbox":"http://patchwork.ozlabs.org/series/499185/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221127/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=NJVmEoc9;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=K3Z+cXPV;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4frXws2VwVz1xv0\n\tfor ; Thu, 09 Apr 2026 05:21:17 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wAYRl-0000a4-Ia; Wed, 08 Apr 2026 15:20:17 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wAY2n-0005jf-0V\n for qemu-devel@nongnu.org; Wed, 08 Apr 2026 14:54:29 -0400","from mx0b-0031df01.pphosted.com ([205.220.180.131])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wAVu0-0006o9-8l\n for qemu-devel@nongnu.org; Wed, 08 Apr 2026 12:37:18 -0400","from pps.filterd (m0279868.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 638GCDdF1073261\n for ; Wed, 8 Apr 2026 16:37:15 GMT","from mail-pg1-f198.google.com (mail-pg1-f198.google.com\n [209.85.215.198])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ddtb382bf-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for ; Wed, 08 Apr 2026 16:37:15 +0000 (GMT)","by mail-pg1-f198.google.com with SMTP id\n 41be03b00d2f7-c7424d91b2dso39073a12.1\n for ; Wed, 08 Apr 2026 09:37:15 -0700 (PDT)","from hu-mathbern-lv.qualcomm.com (Global_NAT1.qualcomm.com.\n [129.46.96.20]) by smtp.gmail.com with ESMTPSA id\n a92af1059eb24-12c1ff43d04sm4082006c88.4.2026.04.08.09.37.12\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Wed, 08 Apr 2026 09:37:12 -0700 (PDT)"],"DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h=\n cc:content-transfer-encoding:date:from:in-reply-to:message-id\n :mime-version:references:subject:to; s=qcppdkim1; bh=Xz1CmgTtPGx\n O7CCCYjV3Yce2C/RGGhA/FnEMzJwczJA=; b=NJVmEoc9CfN6PWNfO0fgvnnR8j3\n Nsa8haSNBS1sMwcoORibkJgUBLD+plZ9+85G1V2+pEztvdXfDKlOg7e+uK6SYDCs\n Q0/c1moP8dD6t5098fpfkbLFrRgJEGdstCOgVT86xogArxB+kw4/r1/WUz+qYvtB\n tQCP1VZnQnuyQm6BhPLCt0DGnU3kMixxKYTzQQp+N2rVOHLpZJtxiukL/lkQUzrA\n wGSmoS3YnSzh9911cOpw9uEV2A6Tahymx6I42Y9yiH/m+Pu5AbPg3YS09BCP3IGc\n Ve/jm7d+cagSjuQh6Hb/vf4UbqhN7p6FwjVzPbeh9/AbqcAheobGXLqDPAA==","v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=oss.qualcomm.com; s=google; t=1775666234; x=1776271034; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=Xz1CmgTtPGxO7CCCYjV3Yce2C/RGGhA/FnEMzJwczJA=;\n b=K3Z+cXPVHWSCVAOmNm0uqRWp8QhINqgsWxGhQJ5zUx1A3nQzBc5V/5ZmvGm6LT/ZId\n Jvnu7G0syJm5yJ1nedARZsWYywbKA2ZSNP+lintfROokKaYVyxTabmGIh7iJ/9zkXhAF\n h0N2TZGU1iz0L1jlXeSAq92tdGhiij+yDUfy3CMX/FANmMrbaxeBkDhTieDOJBU8xrVB\n IfzyLkRPShU0mdyNF/nwIcCB6tF/cMZLTga5Z9ksl05MBLdIN5vxUCGM/j/706AkT3Dd\n C3m3iANoxma7W/sF50Ntrc5eYwGd3L105MJSKHNOaLRsBzjN4l4pkUmhSXO1k0p6NoiU\n arSA=="],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1775666234; x=1776271034;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=Xz1CmgTtPGxO7CCCYjV3Yce2C/RGGhA/FnEMzJwczJA=;\n b=plJh1S7jKAybt1dLn4dSVe+K49PuLNWMMr9fw9lZPfSzK7klXpGAvO9cX/o3x39gSO\n 6GSlr2Ej43QgfVYlbl6Sh6bUpyutOfEZK8s3dsOg/YMk+AkfGZeyEi/KnZ090vU53z5V\n hlqNcRhJjoSkLwxtLoKSe8j7EqWyr/NwzgT7BVUpbu650dq343bcrNM31Lawz4ds35yR\n ysBm4yXFRvWyh97XW1RMfomqpnRVfDOQrKU0WSGQpw6H57KwrfmTiEMQZTx+XTpWpt8G\n +dXV6eBGNQ4ODeOKyDlIPfTcntJyobt3e8fD6r6nNmWVg1MJKvw6Ysf+CJqAb7fxdu+1\n QwKw==","X-Gm-Message-State":"AOJu0Yz7+UbzqPeDgYYEs96oYEXgBLBPZKdwGkL/c3v3x2xvuHhEsL6D\n NeL/PGdMYWDo3T3/5v8SrG6vO0r4qpwbyf1SchsoTviTr6r3JhYchzN+ynurnunTagab7nDB/2O\n VTTd/cPSe7NGkTJ+NTi8S3606EqBDuHA9z6jWDiWjmnw1GaYUMAOb3TBch2cr0BokH0ik","X-Gm-Gg":"AeBDieusKKdy+oBlqSg0EM+duwimEk7QDZCoM3k8d71aSP1DHt6GH2dRYTTpTGhIqvg\n bo72QUcwZXW5vX4n1uNySadglgECR184V13Lbgh956pauNuZIe3/8ErEMrKjoxL3/XDCEWcOlIO\n 3w8P8O8byfJh8uGMF4Mr2arWXl5u5wyM1WkEm5sghlrSBJH8T6wqi4rMNkAx91XaHNgbgQUC2I5\n +ysVkUJEAH39siEnJqVD342qYlhlfrARRnykuyCp4x3C3yd+7CjFWKc/qIE9OjLSSMniJZAB+uT\n n0gdoM7ngcKZrrEGlhpKKoXqpr+6kywtnuoe7Bl2Xaqw8t0A2i2aFsAS+senDm8E/aXRWZ5y5LY\n mtPAWnT3+aD8jSoEhJjSyXU/CbRdW4CSGttnoQp+pHNdKA50Q1w9E6akPMh4P16byUj2N4xH0bV\n 18zjY5gO4j","X-Received":["by 2002:a05:7022:6881:b0:128:dedf:f56d with SMTP id\n a92af1059eb24-12bfb74419bmr11038051c88.24.1775666233641;\n Wed, 08 Apr 2026 09:37:13 -0700 (PDT)","by 2002:a05:7022:6881:b0:128:dedf:f56d with SMTP id\n a92af1059eb24-12bfb74419bmr11038024c88.24.1775666233062;\n Wed, 08 Apr 2026 09:37:13 -0700 (PDT)"],"From":"Matheus Tavares Bernardino ","To":"qemu-devel@nongnu.org","Cc":"richard.henderson@linaro.org, ale@rev.ng, anjo@rev.ng,\n brian.cain@oss.qualcomm.com, ltaylorsimpson@gmail.com,\n marco.liebel@oss.qualcomm.com, philmd@linaro.org,\n quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com","Subject":"[PATCH v3 04/16] hexagon: group cpu configurations in their own\n struct","Date":"Wed, 8 Apr 2026 09:36:55 -0700","Message-Id":"\n ","X-Mailer":"git-send-email 2.37.2","In-Reply-To":"","References":"","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDA4MDE1NCBTYWx0ZWRfX+8glG7gmmDL1\n 5RqBU9ACSp8eg6nIncNWwF5jndCVQkBGfBo6xAUBEn5Jqf1EEm56HLh5pwo6mQhhPtaSGPDNHwu\n Ge5wLtphJP2z+FwP4iYaDvT6FiKx6y9ws+KLKZZFSN1RTBcDSOunucy9XgtsZw5prlmg+rQMOTj\n 8dAGcGm+26VlKmsL0N/H7UXKwk2P4+rtHKfW4BwM970bFAoe33vyI6Zny6/NNVsLH1EESMG99G4\n LjESmQB+x0xbA0UV+IEBr+FRaltYk8Ox2fSEtbPDfptoHTUCTA4mY9WLcpuovnrt0czh+t4/oaA\n PREiBMS1hdRgsUvt4Tr3TrO1DSmYwl4S7sPibQXl1d1mKB0csl26Llvnby0TrgGBVKEOn5Y/vEY\n kpQheWxKv/xONTLRwZnSuspWZFpLRWAzND0VG1JNy8RseS3UjoFcTV0gBofdPia1rtloeMWQ6zq\n hwpcjP7gfBNIElmx7KA==","X-Authority-Analysis":"v=2.4 cv=eKIjSnp1 c=1 sm=1 tr=0 ts=69d6843b cx=c_pps\n a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8\n a=AHWWR7nXwgbOQO2z_T8A:9 a=x9snwWr2DeNwDh03kgHS:22","X-Proofpoint-GUID":"3K7r7gASpZIozAkPxZE9mJ-Cno8dAVPA","X-Proofpoint-ORIG-GUID":"3K7r7gASpZIozAkPxZE9mJ-Cno8dAVPA","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-08_05,2026-04-08_01,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n adultscore=0 impostorscore=0 phishscore=0 priorityscore=1501\n lowpriorityscore=0 clxscore=1015 spamscore=0 suspectscore=0 malwarescore=0\n bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound\n adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000\n definitions=main-2604080154","Received-SPF":"pass client-ip=205.220.180.131;\n envelope-from=matheus.bernardino@oss.qualcomm.com;\n helo=mx0b-0031df01.pphosted.com","X-Spam_score_int":"-27","X-Spam_score":"-2.8","X-Spam_bar":"--","X-Spam_report":"(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"This will be used in a follow up commit.\n\nSigned-off-by: Matheus Tavares Bernardino \n---\n target/hexagon/cpu.h | 10 +++-------\n target/hexagon/cpu_bits.h | 7 +++++++\n target/hexagon/cpu.c | 14 +++++++-------\n target/hexagon/translate.c | 6 +++---\n 4 files changed, 20 insertions(+), 17 deletions(-)","diff":"diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h\nindex 77822a48b6..d28beaa92f 100644\n--- a/target/hexagon/cpu.h\n+++ b/target/hexagon/cpu.h\n@@ -119,19 +119,15 @@ typedef struct HexagonCPUClass {\n ResettablePhases parent_phases;\n } HexagonCPUClass;\n \n+#include \"cpu_bits.h\"\n+\n struct ArchCPU {\n CPUState parent_obj;\n \n CPUHexagonState env;\n-\n- bool lldb_compat;\n- target_ulong lldb_stack_adjust;\n- bool short_circuit;\n- bool ieee_fp_extension;\n+ HexagonCPUConfig cfg;\n };\n \n-#include \"cpu_bits.h\"\n-\n FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1)\n \n G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env,\ndiff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h\nindex 19beca81c0..83d13de569 100644\n--- a/target/hexagon/cpu_bits.h\n+++ b/target/hexagon/cpu_bits.h\n@@ -20,6 +20,13 @@\n \n #include \"qemu/bitops.h\"\n \n+typedef struct HexagonCPUConfig {\n+ bool lldb_compat;\n+ uint32_t lldb_stack_adjust;\n+ bool short_circuit;\n+ bool ieee_fp_extension;\n+} HexagonCPUConfig;\n+\n #define PCALIGN 4\n #define PCALIGN_MASK (PCALIGN - 1)\n \ndiff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c\nindex 8b72a5d3c8..5470d9c7ce 100644\n--- a/target/hexagon/cpu.c\n+++ b/target/hexagon/cpu.c\n@@ -50,11 +50,11 @@ static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model)\n }\n \n static const Property hexagon_cpu_properties[] = {\n- DEFINE_PROP_BOOL(\"lldb-compat\", HexagonCPU, lldb_compat, false),\n- DEFINE_PROP_UNSIGNED(\"lldb-stack-adjust\", HexagonCPU, lldb_stack_adjust, 0,\n- qdev_prop_uint32, target_ulong),\n- DEFINE_PROP_BOOL(\"short-circuit\", HexagonCPU, short_circuit, true),\n- DEFINE_PROP_BOOL(\"ieee-fp\", HexagonCPU, ieee_fp_extension, true),\n+ DEFINE_PROP_BOOL(\"lldb-compat\", HexagonCPU, cfg.lldb_compat, false),\n+ DEFINE_PROP_UNSIGNED(\"lldb-stack-adjust\", HexagonCPU, cfg.lldb_stack_adjust,\n+ 0, qdev_prop_uint32, target_ulong),\n+ DEFINE_PROP_BOOL(\"short-circuit\", HexagonCPU, cfg.short_circuit, true),\n+ DEFINE_PROP_BOOL(\"ieee-fp\", HexagonCPU, cfg.ieee_fp_extension, true),\n };\n \n const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = {\n@@ -77,7 +77,7 @@ const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = {\n static target_ulong adjust_stack_ptrs(CPUHexagonState *env, target_ulong addr)\n {\n HexagonCPU *cpu = env_archcpu(env);\n- target_ulong stack_adjust = cpu->lldb_stack_adjust;\n+ target_ulong stack_adjust = cpu->cfg.lldb_stack_adjust;\n target_ulong stack_start = env->stack_start;\n target_ulong stack_size = 0x10000;\n \n@@ -181,7 +181,7 @@ static void hexagon_dump(CPUHexagonState *env, FILE *f, int flags)\n {\n HexagonCPU *cpu = env_archcpu(env);\n \n- if (cpu->lldb_compat) {\n+ if (cpu->cfg.lldb_compat) {\n /*\n * When comparing with LLDB, it doesn't step through single-cycle\n * hardware loops the same way. So, we just skip them here\ndiff --git a/target/hexagon/translate.c b/target/hexagon/translate.c\nindex fa8f615a9e..ce3af96675 100644\n--- a/target/hexagon/translate.c\n+++ b/target/hexagon/translate.c\n@@ -987,8 +987,8 @@ static void hexagon_tr_init_disas_context(DisasContextBase *dcbase,\n ctx->num_hvx_insns = 0;\n ctx->branch_cond = TCG_COND_NEVER;\n ctx->is_tight_loop = FIELD_EX32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP);\n- ctx->short_circuit = hex_cpu->short_circuit;\n- ctx->ieee_fp_extension = hex_cpu->ieee_fp_extension;\n+ ctx->short_circuit = hex_cpu->cfg.short_circuit;\n+ ctx->ieee_fp_extension = hex_cpu->cfg.ieee_fp_extension;\n }\n \n static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu)\n@@ -1041,7 +1041,7 @@ static void hexagon_tr_translate_packet(DisasContextBase *dcbase, CPUState *cpu)\n * so end the TLB after every packet.\n */\n HexagonCPU *hex_cpu = env_archcpu(env);\n- if (hex_cpu->lldb_compat && qemu_loglevel_mask(CPU_LOG_TB_CPU)) {\n+ if (hex_cpu->cfg.lldb_compat && qemu_loglevel_mask(CPU_LOG_TB_CPU)) {\n ctx->base.is_jmp = DISAS_TOO_MANY;\n }\n }\n","prefixes":["v3","04/16"]}