{"id":2221092,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2221092/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<12d1c25d334b2b97d61b7d1d5b972a89ba235587.1775665981.git.matheus.bernardino@oss.qualcomm.com>","date":"2026-04-08T16:37:07","name":"[v3,16/16] tests/hexagon: add tests for HVX bfloat","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"ed481a5f274c88f6cddc06652421dd37ddde4eac","submitter":{"id":90606,"url":"http://patchwork.ozlabs.org/api/1.0/people/90606/?format=json","name":"Matheus Tavares Bernardino","email":"matheus.bernardino@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/12d1c25d334b2b97d61b7d1d5b972a89ba235587.1775665981.git.matheus.bernardino@oss.qualcomm.com/mbox/","series":[{"id":499185,"url":"http://patchwork.ozlabs.org/api/1.0/series/499185/?format=json","date":"2026-04-08T16:36:53","name":"hexagon: add missing HVX float instructions","version":3,"mbox":"http://patchwork.ozlabs.org/series/499185/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221092/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=Re+OKcOz;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n 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action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Signed-off-by: Matheus Tavares Bernardino \n---\n tests/tcg/hexagon/hex_test.h | 13 +++++++++\n tests/tcg/hexagon/hvx_misc.h | 30 ++++++++++++++++++++\n tests/tcg/hexagon/fp_hvx.c | 41 +++++++++++++++++++++++++++\n tests/tcg/hexagon/fp_hvx_cmp.c | 52 ++++++++++++++++++++++++++++++++++\n tests/tcg/hexagon/fp_hvx_cvt.c | 31 ++++++++++++++++++++\n 5 files changed, 167 insertions(+)","diff":"diff --git a/tests/tcg/hexagon/hex_test.h b/tests/tcg/hexagon/hex_test.h\nindex 79d30ec61c..f86e6e1a69 100644\n--- a/tests/tcg/hexagon/hex_test.h\n+++ b/tests/tcg/hexagon/hex_test.h\n@@ -126,6 +126,19 @@ const uint16_t HF_small_neg = 0x8010;\n const uint16_t HF_any = 0x3c00;\n const uint16_t HF_neg_two = 0xc000;\n \n+const uint16_t BF_INF = 0x7f80;\n+const uint16_t BF_INF_neg = 0xff80;\n+const uint16_t BF_QNaN = 0x7fc0;\n+const uint16_t BF_SNaN = 0x7f81;\n+const uint16_t BF_QNaN_neg = 0xffc0;\n+const uint16_t BF_SNaN_neg = 0xff81;\n+const uint16_t BF_HEX_NaN = 0x7fff;\n+const uint16_t BF_zero = 0x0000;\n+const uint16_t BF_zero_neg = 0x8000;\n+const uint16_t BF_one = 0x3f80;\n+const uint16_t BF_two = 0x4000;\n+const uint16_t BF_four = 0x4080;\n+\n const uint32_t SF_INF = 0x7f800000;\n const uint32_t SF_INF_neg = 0xff800000;\n const uint32_t SF_QNaN = 0x7fc00000;\ndiff --git a/tests/tcg/hexagon/hvx_misc.h b/tests/tcg/hexagon/hvx_misc.h\nindex 43de20da6a..c21ea975c1 100644\n--- a/tests/tcg/hexagon/hvx_misc.h\n+++ b/tests/tcg/hexagon/hvx_misc.h\n@@ -41,6 +41,7 @@ typedef union {\n uint16_t uh[MAX_VEC_SIZE_BYTES / 2];\n uint16_t hf[MAX_VEC_SIZE_BYTES / 2]; /* convenience alias */\n int16_t h[MAX_VEC_SIZE_BYTES / 2];\n+ uint16_t bf[MAX_VEC_SIZE_BYTES / 2];\n uint8_t ub[MAX_VEC_SIZE_BYTES / 1];\n int8_t b[MAX_VEC_SIZE_BYTES / 1];\n } MMVector;\n@@ -73,6 +74,7 @@ CHECK_OUTPUT_FUNC(uh, 2)\n CHECK_OUTPUT_FUNC(hf, 2)\n CHECK_OUTPUT_FUNC(ub, 1)\n CHECK_OUTPUT_FUNC(b, 1)\n+CHECK_OUTPUT_FUNC(bf, 2)\n \n static inline void init_buffers(void)\n {\n@@ -97,6 +99,12 @@ static const uint32_t FP_VALUES[] = {\n };\n #define FP_VALUES_MAX ARRAY_SIZE(FP_VALUES)\n \n+static const uint16_t BF_VALUES[] = {\n+ BF_INF, BF_INF_neg, BF_QNaN, BF_SNaN, BF_QNaN_neg, BF_SNaN_neg,\n+ BF_HEX_NaN, BF_zero, BF_zero_neg, BF_one, BF_two, BF_four,\n+};\n+#define BF_VALUES_MAX ARRAY_SIZE(BF_VALUES)\n+\n static inline void init_buffers_fp(void)\n {\n _Static_assert(BUFSIZE * (MAX_VEC_SIZE_BYTES / 4) >\n@@ -116,6 +124,25 @@ static inline void init_buffers_fp(void)\n }\n }\n \n+static inline void init_buffers_bf(void)\n+{\n+ _Static_assert(BUFSIZE * (MAX_VEC_SIZE_BYTES / 2) >\n+ BF_VALUES_MAX * BF_VALUES_MAX,\n+ \"test arrays can't fit all BF_VALUES combinations\");\n+ int counter1 = 0, counter2 = 0;\n+ for (int i = 0; i < BUFSIZE; i++) {\n+ for (int j = 0; j < MAX_VEC_SIZE_BYTES / 2; j++) {\n+ buffer0[i].bf[j] = BF_VALUES[counter1];\n+ buffer1[i].bf[j] = BF_VALUES[counter2];\n+ counter2++;\n+ if (counter2 == BF_VALUES_MAX) {\n+ counter2 = 0;\n+ counter1 = (counter1 + 1) % BF_VALUES_MAX;\n+ }\n+ }\n+ }\n+}\n+\n #define VEC_OP1(ASM, EL, IN, OUT) \\\n asm(\"v2 = vmem(%0 + #0)\\n\\t\" \\\n \"v2\" #EL \" = \" #ASM \"(v2\" #EL \")\\n\\t\" \\\n@@ -212,10 +239,13 @@ static inline void test_##NAME(bool invert) \\\n \n #define float_sf(x) ({ typeof(x) _x = (x); *((float *)&(_x)); })\n #define float_hf(x) ({ typeof(x) _x = (x); *((_Float16 *) &(_x)); })\n+#define float_bf(x) ({ uint32_t _u = ((uint32_t)(x)) << 16; *((float *)&(_u)); })\n #define raw_sf(x) ({ typeof(x) _x = (x); *((uint32_t *)&(_x)); })\n #define raw_hf(x) ({ typeof(x) _x = (x); *((uint16_t *)&(_x)); })\n+#define raw_bf(x) ({ typeof(x) _x = (x); (uint16_t)(*((uint32_t *)&(_x)) >> 16); })\n #define float_hf_to_sf(x) ((float)x)\n #define bytes_hf 2\n #define bytes_sf 4\n+#define bytes_bf 2\n \n #endif\ndiff --git a/tests/tcg/hexagon/fp_hvx.c b/tests/tcg/hexagon/fp_hvx.c\nindex 46f49c0d3c..f22514b4bf 100644\n--- a/tests/tcg/hexagon/fp_hvx.c\n+++ b/tests/tcg/hexagon/fp_hvx.c\n@@ -29,6 +29,7 @@ int err;\n #define CHECK_NAN(A, DEF_NAN) (isnan(A) ? DEF_NAN : (A))\n #define NAN_SF float_sf(0x7FFFFFFF)\n #define NAN_HF float_hf(0x7FFF)\n+#define NAN_BF float_hf(0x7FFF)\n \n /******************************************************************************\n * Binary operations\n@@ -91,11 +92,43 @@ DEF_TEST_OP_2(vmpy, MULT_HF, hf, hf);\n #define MAX_HF(X, Y) MAX(X, Y, NAN_HF)\n #define MIN_SF(X, Y) MIN(X, Y, NAN_SF)\n #define MAX_SF(X, Y) MAX(X, Y, NAN_SF)\n+#define MIN_BF(X, Y) MIN(X, Y, NAN_BF)\n+#define MAX_BF(X, Y) MAX(X, Y, NAN_BF)\n \n DEF_TEST_OP_2(vfmin, MIN_SF, sf, sf);\n DEF_TEST_OP_2(vfmax, MAX_SF, sf, sf);\n DEF_TEST_OP_2(vfmin, MIN_HF, hf, hf);\n DEF_TEST_OP_2(vfmax, MAX_HF, hf, hf);\n+DEF_TEST_OP_2(vmin, MIN_BF, bf, bf);\n+DEF_TEST_OP_2(vmax, MAX_BF, bf, bf);\n+\n+#define DEF_TEST_OP_2_INTERLEAVED(vop, op, type_res, type_arg) \\\n+ static void test_##vop##_##type_res##_##type_arg(void) \\\n+ { \\\n+ memset(expect, 0xff, sizeof(expect)); \\\n+ memset(output, 0xff, sizeof(output)); \\\n+ for (int i = 0; i < BUFSIZE / 2; i++) { \\\n+ HVX_VectorPair *hvx_output = (HVX_VectorPair *)&output[2 * i]; \\\n+ HVX_Vector hvx_buffer0 = *(HVX_Vector *)&buffer0[i]; \\\n+ HVX_Vector hvx_buffer1 = *(HVX_Vector *)&buffer1[i]; \\\n+ *hvx_output = \\\n+ Q6_W##type_res##_##vop##_V##type_arg##V##type_arg(hvx_buffer0, \\\n+ hvx_buffer1); \\\n+ for (int j = 0; j < MAX_VEC_SIZE_BYTES / bytes_##type_res; j++) { \\\n+ expect[2 * i].type_res[j] = \\\n+ raw_##type_res(op(float_##type_arg(buffer0[i].type_arg[2 * j]), \\\n+ float_##type_arg(buffer1[i].type_arg[2 * j]))); \\\n+ expect[2 * i + 1].type_res[j] = \\\n+ raw_##type_res(op(float_##type_arg(buffer0[i].type_arg[2 * j + 1]), \\\n+ float_##type_arg(buffer1[i].type_arg[2 * j + 1]))); \\\n+ } \\\n+ } \\\n+ check_output_##type_res(__LINE__, BUFSIZE); \\\n+ }\n+\n+DEF_TEST_OP_2_INTERLEAVED(vadd, SUM_SF, sf, bf);\n+DEF_TEST_OP_2_INTERLEAVED(vsub, SUB_SF, sf, bf);\n+DEF_TEST_OP_2_INTERLEAVED(vmpy, MULT_SF, sf, bf);\n \n /******************************************************************************\n * Other tests\n@@ -180,6 +213,14 @@ int main(void)\n test_vfmax_sf_sf();\n test_vfmax_hf_hf();\n \n+ /* bfloat */\n+ init_buffers_bf();\n+ test_vmin_bf_bf();\n+ test_vmax_bf_bf();\n+ test_vadd_sf_bf();\n+ test_vsub_sf_bf();\n+ test_vmpy_sf_bf();\n+\n puts(err ? \"FAIL\" : \"PASS\");\n return err ? 1 : 0;\n }\ndiff --git a/tests/tcg/hexagon/fp_hvx_cmp.c b/tests/tcg/hexagon/fp_hvx_cmp.c\nindex c4e1c81ce5..4417e736f9 100644\n--- a/tests/tcg/hexagon/fp_hvx_cmp.c\n+++ b/tests/tcg/hexagon/fp_hvx_cmp.c\n@@ -22,9 +22,11 @@ int err;\n \n #define MAX_TESTS_hf (MAX_VEC_SIZE_BYTES / 2)\n #define MAX_TESTS_sf (MAX_VEC_SIZE_BYTES / 4)\n+#define MAX_TESTS_bf (MAX_VEC_SIZE_BYTES / 4)\n \n #define TRUE_MASK_sf 0xffffffff\n #define TRUE_MASK_hf 0xffff\n+#define TRUE_MASK_bf 0xffff\n \n static const char *comparisons[MAX_TESTS_sf][2];\n static HVX_Vector *hvx_output = (HVX_Vector *)&output[0];\n@@ -160,6 +162,55 @@ static void test_cmp_hf(void)\n CHECK(hf, 2);\n }\n \n+\n+static void test_cmp_bf(void)\n+{\n+ /*\n+ * General ordering for bf:\n+ * QNaN > SNaN > +Inf > numbers > -Inf > SNaN_neg > QNaN_neg\n+ */\n+\n+ /* Test equality */\n+ PREP_TEST();\n+ ADD_TEST_CMP(bf, 0, 0, false);\n+ ADD_TEST_CMP(bf, BF_SNaN, BF_SNaN, false);\n+ CHECK(bf, 2);\n+\n+ /* Common numbers */\n+ PREP_TEST();\n+ TEST_CMP_GT(bf, raw_hf((_Float16)2.2), raw_hf((_Float16)2.1));\n+ TEST_CMP_GT(bf, raw_hf((_Float16)0), raw_hf((_Float16)-2.2));\n+ CHECK(bf, 2);\n+\n+ /* Infinity vs Infinity/NaN */\n+ PREP_TEST();\n+ TEST_CMP_GT(bf, BF_QNaN, BF_INF);\n+ TEST_CMP_GT(bf, BF_SNaN, BF_INF);\n+ TEST_CMP_GT(bf, BF_INF, BF_INF_neg);\n+ TEST_CMP_GT(bf, BF_INF, BF_SNaN_neg);\n+ TEST_CMP_GT(bf, BF_INF, BF_QNaN_neg);\n+ TEST_CMP_GT(bf, BF_INF_neg, BF_SNaN_neg);\n+ TEST_CMP_GT(bf, BF_INF_neg, BF_QNaN_neg);\n+ TEST_CMP_GT(bf, BF_SNaN, BF_INF_neg);\n+ TEST_CMP_GT(bf, BF_QNaN, BF_INF_neg);\n+ CHECK(bf, 2);\n+\n+ /* NaN vs NaN */\n+ PREP_TEST();\n+ TEST_CMP_GT(bf, BF_QNaN, BF_SNaN);\n+ TEST_CMP_GT(bf, BF_SNaN, BF_SNaN_neg);\n+ TEST_CMP_GT(bf, BF_SNaN_neg, BF_QNaN_neg);\n+ CHECK(bf, 2);\n+\n+ /* NaN vs non-NaN */\n+ PREP_TEST();\n+ TEST_CMP_GT(bf, BF_QNaN, BF_one);\n+ TEST_CMP_GT(bf, BF_SNaN, BF_one);\n+ TEST_CMP_GT(bf, BF_one, BF_QNaN_neg);\n+ TEST_CMP_GT(bf, BF_one, BF_SNaN_neg);\n+ CHECK(bf, 2);\n+}\n+\n static void test_cmp_variants(void)\n {\n HVX_VectorPred true_pred, false_pred, pred;\n@@ -220,6 +271,7 @@ int main(void)\n \n test_cmp_sf();\n test_cmp_hf();\n+ test_cmp_bf();\n test_cmp_variants();\n \n puts(err ? \"FAIL\" : \"PASS\");\ndiff --git a/tests/tcg/hexagon/fp_hvx_cvt.c b/tests/tcg/hexagon/fp_hvx_cvt.c\nindex 71c3f0fd4f..bd8d39d6b6 100644\n--- a/tests/tcg/hexagon/fp_hvx_cvt.c\n+++ b/tests/tcg/hexagon/fp_hvx_cvt.c\n@@ -19,6 +19,8 @@ int err;\n #include \"hvx_misc.h\"\n #include \"hex_test.h\"\n \n+#define NAN_BF 0x7FFF\n+\n #define TEST_EXP(TO, FROM, VAL, EXP) do { \\\n ((MMVector *)&buffer)->FROM[index] = VAL; \\\n expect[0].TO[index] = EXP; \\\n@@ -172,6 +174,34 @@ DEF_TEST_VCONV(sf, w, { \\\n TEST_EXP(sf, w, 16777219, raw_sf((float)16777220)); /* rounds UP */ \\\n })\n \n+#define TEST_EXP_BF(VAL, EXP) do { \\\n+ ((MMVector *)&buffers[1])->sf[index] = VAL; \\\n+ ((MMVector *)&buffers[0])->sf[index] = VAL; \\\n+ expect[0].bf[2 * index] = EXP; \\\n+ expect[0].bf[2 * index + 1] = EXP; \\\n+ index++; \\\n+} while (0)\n+\n+static void test_vconv_bf_sf(void)\n+{\n+ HVX_Vector *hvx_output = (HVX_Vector *)&output[0];\n+ HVX_Vector buffers[2];\n+ int index = 0;\n+ memset(&buffers, 0, sizeof(buffers));\n+ memset(expect, 0, sizeof(expect));\n+\n+ TEST_EXP_BF(SF_QNaN, NAN_BF);\n+ TEST_EXP_BF(SF_SNaN, NAN_BF);\n+ TEST_EXP_BF(SF_QNaN_neg, NAN_BF);\n+ TEST_EXP_BF(SF_INF, BF_INF);\n+ TEST_EXP_BF(SF_INF_neg, BF_INF_neg);\n+ TEST_EXP_BF(SF_one, BF_one);\n+ TEST_EXP_BF(SF_zero_neg, BF_zero_neg);\n+\n+ *hvx_output = Q6_Vbf_vcvt_VsfVsf(buffers[0], buffers[1]);\n+ check_output_hf(__LINE__, 1);\n+}\n+\n int main(void)\n {\n test_vcvt_uh_hf();\n@@ -182,6 +212,7 @@ int main(void)\n test_vconv_sf_w();\n test_vconv_h_hf();\n test_vconv_hf_h();\n+ test_vconv_bf_sf();\n \n puts(err ? \"FAIL\" : \"PASS\");\n return err ? 1 : 0;\n","prefixes":["v3","16/16"]}