{"id":2221078,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2221078/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260408041953.1899532-13-brian.cain@oss.qualcomm.com>","date":"2026-04-08T04:19:37","name":"[v4,12/28] target/hexagon: Implement hexagon_tlb_fill()","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"77ec9479ca39fd66f9e542b281cee872f9658eb9","submitter":{"id":89839,"url":"http://patchwork.ozlabs.org/api/1.0/people/89839/?format=json","name":"Brian Cain","email":"brian.cain@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260408041953.1899532-13-brian.cain@oss.qualcomm.com/mbox/","series":[{"id":499179,"url":"http://patchwork.ozlabs.org/api/1.0/series/499179/?format=json","date":"2026-04-08T04:19:31","name":"Hexagon system emulation - Part 2/3","version":4,"mbox":"http://patchwork.ozlabs.org/series/499179/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221078/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=eh2yzwpV;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=cT9027Ig;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (unknown [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4frX9y2Thjz20wy\n\tfor ; Thu, 09 Apr 2026 04:47:34 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wAXqT-0004E1-9X; Wed, 08 Apr 2026 14:41:45 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wAXqH-0002hG-11\n for qemu-devel@nongnu.org; Wed, 08 Apr 2026 14:41:33 -0400","from mx0b-0031df01.pphosted.com ([205.220.180.131])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wAKP4-0005al-En\n for qemu-devel@nongnu.org; Wed, 08 Apr 2026 00:20:37 -0400","from pps.filterd (m0279871.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 637NfdAo1259461\n for ; Wed, 8 Apr 2026 04:20:22 GMT","from mail-dl1-f71.google.com (mail-dl1-f71.google.com\n [74.125.82.71])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ddbttrqpv-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for ; Wed, 08 Apr 2026 04:20:22 +0000 (GMT)","by mail-dl1-f71.google.com with SMTP id\n a92af1059eb24-1276e71652fso3470660c88.0\n for ; Tue, 07 Apr 2026 21:20:21 -0700 (PDT)","from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com.\n [129.46.96.20]) by smtp.gmail.com with ESMTPSA id\n a92af1059eb24-12c14a371b1sm6480362c88.13.2026.04.07.21.20.19\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Tue, 07 Apr 2026 21:20:19 -0700 (PDT)"],"DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h=\n cc:content-transfer-encoding:content-type:date:from:in-reply-to\n :message-id:mime-version:references:subject:to; s=qcppdkim1; bh=\n gDbVyMRCmszdUrQpfq4kD840ZbzWrxWbhRin4jc7a80=; b=eh2yzwpVwH6TPvS1\n mxUYoVwk1yR69EQjgQ3rT12k/mTIRKq2NKk9fX3uU9ORD9M7iY7Uoc2E8GaEQwsq\n GHaf6aEpCrBvEcXqkz1KRubMJI1OKdCCIym2XBOg5Tcb5Bw5BXpMkPo1JKbjrS5j\n fEUuyTHI/G7A/ljVdtpoCzk4fFpPN6EmWKxHPBKcg+R85/L4f3t+Hu7f4DyJcAzo\n V6fv+7Z07bkcI0sEYGXEYMy0hKUY+snioXWSrDIC6V75z2rW7CxzTYZVNtd7+Z0I\n Q0okvK5yzJaa78ruogTdW6tjtqFLg2pIlvRKFXRNgvZSsMhbV+Olm8KHLp5BZHz1\n 2DNinA==","v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=oss.qualcomm.com; s=google; t=1775622021; x=1776226821; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=gDbVyMRCmszdUrQpfq4kD840ZbzWrxWbhRin4jc7a80=;\n b=cT9027IgIUl959LtbNOwFMzOnk4SgbyFzlSDP7nSRk1/z6eD3Yzvzm19qyEdmzrc/R\n ACZIStkmMt9J8MZF+LZvLM4mrg0Hodnb4+9XhonkrlizxmbKbm1l+CNJne8wMwPKTxQq\n IcbNNEahnnU0g7QeTGe9QL9nEZIwDA//LUdYJ4ingPqDxitYxwBEFJczl2PgcB3/ybwp\n 7rqL90jmv6dOBGcRWwAlWun4pJP/YXq/Uzu9m7xQpm3546rrd3NJ20niufRgk746S8oI\n Yhhq1iARv30pAqKTUBhuk3+d/fa6NYNlcjlWAdpEp1sdIwSVWUQRyat9MyDaHFafVtyA\n UGRw=="],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1775622021; x=1776226821;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=gDbVyMRCmszdUrQpfq4kD840ZbzWrxWbhRin4jc7a80=;\n b=mvAWYJFzAdFfoiO/Dll67CNihodw+gALLmMmq32LBwnpTcaO33HZwfDQv/e1x3yrpm\n +YywB0QIWyfYiDSVrfv+IEZkW+CeuANLRWQ1YOVH5X1KJk0PxMHl5HqJ0sBcvdQnxaU0\n LfxeF/kO025/B08P0bjWG5vWD7/XhcXjabliJqy20I467a5XWGFFhPsDAhCieDD3M9Xb\n ReUgoXWuEaLvk0MSF+0eii0HPSipZiL19olfrBBsYL/Fv0m9nrv9/QKyWaL8XUFSU831\n h90+alK062HYXki353SLLR/oHTYzr2lKjTEMPMKfwqU84hKAKFSYa+HHochbbRFG1OwB\n 2xsw==","X-Gm-Message-State":"AOJu0YwURfjORLRUEPnh4cfyvWIkkCKjRjVDY3sEGM5/itklDxLyBkqd\n nU8G4Fzzw2E/k31iFBetY7bHHxhj27yp2BFWtPnb3o7WwGy/js0ED4r7aAMD8pD9WMFOIdOf5Bd\n UzRysmdTXvcbvfiuG6qwZH59KtLwjTOjqDIGEJ279jGvLpBGMMkuGr0ypLNsgjypNNQ==","X-Gm-Gg":"AeBDietw0ZKlDRxC5jnWz5AL3mqoaR+hxOrTC7NZOCNA/UBNjNpvagsIyXQ8+OEg/3g\n MA1fUf14vHab034uaghCNHKTChkOs4/uXehCqxenGLayTxMfA9hpBz+kLTcZkTkQBymm8kpjc7z\n mNYzL8zdNtUh848bK1sXUcJ+/dkysX72PrgZ0qD4uDaf13aeuy4KjDdi+v0rIJ5r+guri7lyfiq\n i2rVXoAqEfWZnU/HVQ/gL3LPZYj4NcdMs4ETj5KRT9YuiMYVFMeF708sJGAWq7Owschg9YTn4tX\n ya1RkPd/ngyYj4uqj/QylYHhD+CML8GZy1zcrpe3t7ZNqQMS+cAcY9TygkVfhYCX9PojhIDNAkj\n cT5DCTIh0nSu+FyquY5kr0x6jsr2TVt58j52Eb7WEauYAkOwJFK/AH4M2RIL/NtshD5xEUA==","X-Received":["by 2002:a05:7022:4585:b0:128:d4db:4478 with SMTP id\n a92af1059eb24-12bfb75688cmr9259458c88.24.1775622020913;\n Tue, 07 Apr 2026 21:20:20 -0700 (PDT)","by 2002:a05:7022:4585:b0:128:d4db:4478 with SMTP id\n a92af1059eb24-12bfb75688cmr9259445c88.24.1775622020345;\n Tue, 07 Apr 2026 21:20:20 -0700 (PDT)"],"From":"Brian Cain ","To":"qemu-devel@nongnu.org","Cc":"brian.cain@oss.qualcomm.com, philmd@linaro.org, ltaylorsimpson@gmail.com,\n matheus.bernardino@oss.qualcomm.com, marco.liebel@oss.qualcomm.com,\n quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com, ale@rev.ng,\n anjo@rev.ng, Brian Cain ","Subject":"[PATCH v4 12/28] target/hexagon: Implement hexagon_tlb_fill()","Date":"Tue, 7 Apr 2026 21:19:37 -0700","Message-Id":"<20260408041953.1899532-13-brian.cain@oss.qualcomm.com>","X-Mailer":"git-send-email 2.34.1","In-Reply-To":"<20260408041953.1899532-1-brian.cain@oss.qualcomm.com>","References":"<20260408041953.1899532-1-brian.cain@oss.qualcomm.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","X-Proofpoint-ORIG-GUID":"-0kAVQfVeFzNu_J5KZminXivoTBvTS2j","X-Proofpoint-GUID":"-0kAVQfVeFzNu_J5KZminXivoTBvTS2j","X-Authority-Analysis":"v=2.4 cv=TOt1jVla c=1 sm=1 tr=0 ts=69d5d786 cx=c_pps\n a=JYo30EpNSr/tUYqK9jHPoA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22\n a=COk6AnOGAAAA:8 a=pGLkceISAAAA:8 a=EUspDBNiAAAA:8 a=yz7b9sy1sBSXNk6fZdQA:9\n a=QEXdDO2ut3YA:10 a=Fk4IpSoW4aLDllm1B1p-:22 a=TjNXssC_j7lpFel5tvFf:22","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDA4MDAzNSBTYWx0ZWRfX+mffuh+7ZKjP\n A7EU82Flv5seFCFMI50S0eisjPBQCTrJI2kuQ9UACtDX+Kl2tExiBh6JWSmEcgEAbukLoajlSdk\n TCveHoTEj66UPvILnUNj3fvyMJJ8nB4Xg2LpxZRzX3KJjFTNv2NyCIVsUGbFtpiRCI6BX/rIIFY\n /SNTTo48K3MwSEL4Q8PuXDTVWeiSn0WwyckT9LiKl8/s09rjK+p521gVfYlH7yT7sKGsQB6nWRb\n qY8CcYd7oDM9+NEwtJH7AtdyGtTkipQNcDEbXsZy7Uhsqgg7gVJnlTXj3N7GvaWNJ6/10LrHsPL\n H69qxvaGt247HK67kC3xnHL5g1E4cPnmSFdhYsb9o4yLdD4KbPmOQnXDnfp9y4pkQ/0JOMbGr2P\n +wGeLfYJUnIptu0hQJ137P58B5ZMjfX8u79pZZb1LtLhc404OJS/opQLZp0tlXmdo9+POQU0PmH\n j1mSyxMixOuf+nXUJCw==","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-08_02,2026-04-07_05,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n malwarescore=0 suspectscore=0 spamscore=0 adultscore=0 impostorscore=0\n lowpriorityscore=0 phishscore=0 bulkscore=0 clxscore=1015 priorityscore=1501\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604080035","Received-SPF":"pass client-ip=205.220.180.131;\n envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com","X-Spam_score_int":"-27","X-Spam_score":"-2.8","X-Spam_bar":"--","X-Spam_report":"(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Brian Cain \n\nReviewed-by: Taylor Simpson \nSigned-off-by: Brian Cain \n---\n target/hexagon/cpu.c | 135 +++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 135 insertions(+)","diff":"diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c\nindex adae667293d..098a3918c94 100644\n--- a/target/hexagon/cpu.c\n+++ b/target/hexagon/cpu.c\n@@ -38,6 +38,8 @@\n #include \"qemu/main-loop.h\"\n #include \"hex_interrupts.h\"\n #include \"exec/cpu-interrupt.h\"\n+#include \"exec/target_page.h\"\n+#include \"hw/hexagon/hexagon_globalreg.h\"\n #endif\n \n static void hexagon_v66_cpu_init(Object *obj) { }\n@@ -471,6 +473,138 @@ static void hexagon_cpu_init(Object *obj)\n }\n \n #ifndef CONFIG_USER_ONLY\n+static bool get_physical_address(CPUHexagonState *env, hwaddr *phys, int *prot,\n+ uint64_t *size, int32_t *excp,\n+ uint32_t address,\n+ MMUAccessType access_type, int mmu_idx)\n+\n+{\n+ if (hexagon_cpu_mmu_enabled(env)) {\n+ return hex_tlb_find_match(env, address, access_type, phys, prot, size,\n+ excp, mmu_idx);\n+ } else {\n+ *phys = address & 0xFFFFFFFF;\n+ *prot = PAGE_VALID | PAGE_READ | PAGE_WRITE | PAGE_EXEC;\n+ *size = TARGET_PAGE_SIZE;\n+ return true;\n+ }\n+}\n+\n+/* qemu seems to only want to know about TARGET_PAGE_SIZE pages */\n+static void find_qemu_subpage(vaddr *addr, hwaddr *phys, uint64_t page_size)\n+{\n+ vaddr page_start = *addr & ~((vaddr)(page_size - 1));\n+ vaddr offset = ((*addr - page_start) / TARGET_PAGE_SIZE) * TARGET_PAGE_SIZE;\n+ *addr = page_start + offset;\n+ *phys += offset;\n+}\n+\n+\n+#define INVALID_BADVA 0xbadabada\n+\n+static void set_badva_regs(CPUHexagonState *env, uint32_t VA, int slot,\n+ MMUAccessType access_type)\n+{\n+ env->t_sreg[HEX_SREG_BADVA] = VA;\n+\n+ if (access_type == MMU_INST_FETCH || slot == 0) {\n+ env->t_sreg[HEX_SREG_BADVA0] = VA;\n+ env->t_sreg[HEX_SREG_BADVA1] = INVALID_BADVA;\n+ SET_SSR_FIELD(env, SSR_V0, 1);\n+ SET_SSR_FIELD(env, SSR_V1, 0);\n+ SET_SSR_FIELD(env, SSR_BVS, 0);\n+ } else if (slot == 1) {\n+ env->t_sreg[HEX_SREG_BADVA0] = INVALID_BADVA;\n+ env->t_sreg[HEX_SREG_BADVA1] = VA;\n+ SET_SSR_FIELD(env, SSR_V0, 0);\n+ SET_SSR_FIELD(env, SSR_V1, 1);\n+ SET_SSR_FIELD(env, SSR_BVS, 1);\n+ } else {\n+ g_assert_not_reached();\n+ }\n+}\n+\n+static void raise_tlbmiss_exception(CPUState *cs, uint32_t VA, int slot,\n+ MMUAccessType access_type)\n+{\n+ CPUHexagonState *env = cpu_env(cs);\n+\n+ set_badva_regs(env, VA, slot, access_type);\n+\n+ switch (access_type) {\n+ case MMU_INST_FETCH:\n+ cs->exception_index = HEX_EVENT_TLB_MISS_X;\n+ if ((VA & ~TARGET_PAGE_MASK) == 0) {\n+ env->cause_code = HEX_CAUSE_TLBMISSX_CAUSE_NEXTPAGE;\n+ } else {\n+ env->cause_code = HEX_CAUSE_TLBMISSX_CAUSE_NORMAL;\n+ }\n+ break;\n+ case MMU_DATA_LOAD:\n+ cs->exception_index = HEX_EVENT_TLB_MISS_RW;\n+ env->cause_code = HEX_CAUSE_TLBMISSRW_CAUSE_READ;\n+ break;\n+ case MMU_DATA_STORE:\n+ cs->exception_index = HEX_EVENT_TLB_MISS_RW;\n+ env->cause_code = HEX_CAUSE_TLBMISSRW_CAUSE_WRITE;\n+ break;\n+ }\n+}\n+\n+static void raise_perm_exception(CPUState *cs, uint32_t VA, int slot,\n+ MMUAccessType access_type, int32_t excp)\n+{\n+ CPUHexagonState *env = cpu_env(cs);\n+\n+ set_badva_regs(env, VA, slot, access_type);\n+ cs->exception_index = excp;\n+}\n+\n+static const char *access_type_names[] = { \"MMU_DATA_LOAD \", \"MMU_DATA_STORE\",\n+ \"MMU_INST_FETCH\" };\n+\n+static const char *mmu_idx_names[] = { \"MMU_USER_IDX\", \"MMU_GUEST_IDX\",\n+ \"MMU_KERNEL_IDX\" };\n+\n+static bool hexagon_tlb_fill(CPUState *cs, vaddr address, int size,\n+ MMUAccessType access_type, int mmu_idx, bool probe,\n+ uintptr_t retaddr)\n+{\n+ CPUHexagonState *env = cpu_env(cs);\n+ int slot = 0;\n+ hwaddr phys;\n+ int prot = 0;\n+ uint64_t page_size = 0;\n+ int32_t excp = 0;\n+ bool ret = 0;\n+\n+ qemu_log_mask(\n+ CPU_LOG_MMU,\n+ \"%s: tid = 0x%\" PRIx32 \", pc = 0x%08\" PRIx32 \", vaddr = 0x%08\" VADDR_PRIx\n+ \", size = %d, %s,\\tprobe = %d, %s\\n\",\n+ __func__, env->threadId, env->gpr[HEX_REG_PC], address, size,\n+ access_type_names[access_type], probe, mmu_idx_names[mmu_idx]);\n+ ret = get_physical_address(env, &phys, &prot, &page_size, &excp, address,\n+ access_type, mmu_idx);\n+ if (ret) {\n+ if (!excp) {\n+ find_qemu_subpage(&address, &phys, page_size);\n+ tlb_set_page(cs, address, phys, prot, mmu_idx, TARGET_PAGE_SIZE);\n+ return ret;\n+ }\n+ if (probe) {\n+ return false;\n+ }\n+ raise_perm_exception(cs, address, slot, access_type, excp);\n+ do_raise_exception(env, cs->exception_index, env->gpr[HEX_REG_PC],\n+ retaddr);\n+ }\n+ if (probe) {\n+ return false;\n+ }\n+ raise_tlbmiss_exception(cs, address, slot, access_type);\n+ do_raise_exception(env, cs->exception_index, env->gpr[HEX_REG_PC], retaddr);\n+}\n \n static bool hexagon_cpu_exec_interrupt(CPUState *cs, int interrupt_request)\n {\n@@ -513,6 +647,7 @@ static const TCGCPUOps hexagon_tcg_ops = {\n .cpu_exec_interrupt = hexagon_cpu_exec_interrupt,\n .pointer_wrap = hexagon_pointer_wrap,\n .cpu_exec_reset = cpu_reset,\n+ .tlb_fill = hexagon_tlb_fill,\n #endif /* !CONFIG_USER_ONLY */\n };\n \n","prefixes":["v4","12/28"]}