{"id":2221072,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2221072/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<42b4b2d1c61637d9fd951f05371fad452d9af77e.1775665981.git.matheus.bernardino@oss.qualcomm.com>","date":"2026-04-08T16:36:57","name":"[v3,06/16] target/hexagon: add v68 HVX IEEE float arithmetic insns","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"89a43c21b0c30dedd7b66214acc06a6a42238ba2","submitter":{"id":90606,"url":"http://patchwork.ozlabs.org/api/1.0/people/90606/?format=json","name":"Matheus Tavares Bernardino","email":"matheus.bernardino@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/42b4b2d1c61637d9fd951f05371fad452d9af77e.1775665981.git.matheus.bernardino@oss.qualcomm.com/mbox/","series":[{"id":499185,"url":"http://patchwork.ozlabs.org/api/1.0/series/499185/?format=json","date":"2026-04-08T16:36:53","name":"hexagon: add missing HVX float instructions","version":3,"mbox":"http://patchwork.ozlabs.org/series/499185/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221072/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=QDLKKoJO;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n 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Apr 2026 09:37:15 -0700 (PDT)","by 2002:a05:7022:10d:b0:12a:7181:2f1c with SMTP id\n a92af1059eb24-12bfb7452bcmr11882482c88.17.1775666235044;\n Wed, 08 Apr 2026 09:37:15 -0700 (PDT)"],"From":"Matheus Tavares Bernardino ","To":"qemu-devel@nongnu.org","Cc":"richard.henderson@linaro.org, ale@rev.ng, anjo@rev.ng,\n brian.cain@oss.qualcomm.com, ltaylorsimpson@gmail.com,\n marco.liebel@oss.qualcomm.com, philmd@linaro.org,\n quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com","Subject":"[PATCH v3 06/16] target/hexagon: add v68 HVX IEEE float arithmetic\n insns","Date":"Wed, 8 Apr 2026 09:36:57 -0700","Message-Id":"\n <42b4b2d1c61637d9fd951f05371fad452d9af77e.1775665981.git.matheus.bernardino@oss.qualcomm.com>","X-Mailer":"git-send-email 2.37.2","In-Reply-To":"","References":"","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDA4MDE1NCBTYWx0ZWRfXw/I+t6CGDT8U\n iOJOXBJKDa9zQLVyelGOqHuSMQnilbwUz2kXpCYlc/fGj+DA85nxmIUwO2JGARpU+gceRlnz9Ck\n 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action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Add HVX IEEE floating-point arithmetic instructions:\n- vmpy_sf_sf, vmpy_sf_hf, vmpy_hf_hf: multiply operations\n- vdmpy_sf_hf: dot-product multiply\n- vmpy_sf_hf_acc, vmpy_hf_hf_acc, vdmpy_sf_hf_acc: multiply-accumulate\n- vadd_sf_sf, vsub_sf_sf, vadd_sf_hf, vsub_sf_hf: add/sub with sf output\n- vadd_hf_hf, vsub_hf_hf: add/sub with hf output\n\nSigned-off-by: Matheus Tavares Bernardino \n---\n target/hexagon/cpu.h | 1 +\n target/hexagon/mmvec/hvx_ieee_fp.h | 18 ++++\n target/hexagon/mmvec/macros.h | 1 +\n target/hexagon/mmvec/mmvec.h | 2 +\n target/hexagon/attribs_def.h.inc | 4 +\n target/hexagon/arch.c | 8 ++\n target/hexagon/cpu.c | 3 +\n target/hexagon/mmvec/hvx_ieee_fp.c | 21 ++++\n target/hexagon/hex_common.py | 1 +\n target/hexagon/imported/mmvec/encode_ext.def | 18 ++++\n target/hexagon/imported/mmvec/ext.idef | 101 +++++++++++++++++++\n target/hexagon/meson.build | 1 +\n 12 files changed, 179 insertions(+)\n create mode 100644 target/hexagon/mmvec/hvx_ieee_fp.h\n create mode 100644 target/hexagon/mmvec/hvx_ieee_fp.c","diff":"diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h\nindex d28beaa92f..5a008d1949 100644\n--- a/target/hexagon/cpu.h\n+++ b/target/hexagon/cpu.h\n@@ -87,6 +87,7 @@ typedef struct CPUArchState {\n MemLog mem_log_stores[STORES_MAX];\n \n float_status fp_status;\n+ float_status hvx_fp_status;\n \n target_ulong llsc_addr;\n target_ulong llsc_val;\ndiff --git a/target/hexagon/mmvec/hvx_ieee_fp.h b/target/hexagon/mmvec/hvx_ieee_fp.h\nnew file mode 100644\nindex 0000000000..75008deb3b\n--- /dev/null\n+++ b/target/hexagon/mmvec/hvx_ieee_fp.h\n@@ -0,0 +1,18 @@\n+/*\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#ifndef HEXAGON_HVX_IEEE_H\n+#define HEXAGON_HVX_IEEE_H\n+\n+#include \"fpu/softfloat.h\"\n+\n+#define f16_to_f32(A) float16_to_float32((A), true, &env->hvx_fp_status)\n+\n+float32 fp_mult_sf_hf(float16 a1, float16 a2, float_status *fp_status);\n+float32 fp_vdmpy(float16 a1, float16 a2, float16 a3, float16 a4,\n+ float_status *fp_status);\n+\n+#endif\ndiff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h\nindex c7840fbf2e..ac709d8993 100644\n--- a/target/hexagon/mmvec/macros.h\n+++ b/target/hexagon/mmvec/macros.h\n@@ -23,6 +23,7 @@\n #include \"mmvec/system_ext_mmvec.h\"\n #include \"accel/tcg/getpc.h\"\n #include \"accel/tcg/probe.h\"\n+#include \"mmvec/hvx_ieee_fp.h\"\n \n #ifndef QEMU_GENERATE\n #define VdV (*(MMVector *restrict)(VdV_void))\ndiff --git a/target/hexagon/mmvec/mmvec.h b/target/hexagon/mmvec/mmvec.h\nindex 52d470709c..31909303b5 100644\n--- a/target/hexagon/mmvec/mmvec.h\n+++ b/target/hexagon/mmvec/mmvec.h\n@@ -38,6 +38,8 @@ typedef union {\n int16_t h[MAX_VEC_SIZE_BYTES / 2];\n uint8_t ub[MAX_VEC_SIZE_BYTES / 1];\n int8_t b[MAX_VEC_SIZE_BYTES / 1];\n+ float32 sf[MAX_VEC_SIZE_BYTES / 4];\n+ float16 hf[MAX_VEC_SIZE_BYTES / 2];\n } MMVector;\n \n typedef union {\ndiff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.h.inc\nindex c85cd5d17c..d3c4bf6301 100644\n--- a/target/hexagon/attribs_def.h.inc\n+++ b/target/hexagon/attribs_def.h.inc\n@@ -175,6 +175,10 @@ DEF_ATTRIB(RESTRICT_LATEPRED, \"Predicate can not be used as a .new.\", \"\", \"\")\n \n /* HVX IEEE FP extension attributes */\n DEF_ATTRIB(HVX_IEEE_FP, \"HVX IEEE FP extension instruction\", \"\", \"\")\n+DEF_ATTRIB(HVX_IEEE_FP_ACC, \"HVX IEEE FP accumulate instruction\", \"\", \"\")\n+DEF_ATTRIB(HVX_IEEE_FP_OUT_16, \"HVX IEEE FP 16-bit output\", \"\", \"\")\n+DEF_ATTRIB(HVX_IEEE_FP_OUT_32, \"HVX IEEE FP 32-bit output\", \"\", \"\")\n+DEF_ATTRIB(CVI_VX_NO_TMP_LD, \"HVX multiply without tmp load\", \"\", \"\")\n \n /* Keep this as the last attribute: */\n DEF_ATTRIB(ZZ_LASTATTRIB, \"Last attribute in the file\", \"\", \"\")\ndiff --git a/target/hexagon/arch.c b/target/hexagon/arch.c\nindex e17e714a6a..358aa71e03 100644\n--- a/target/hexagon/arch.c\n+++ b/target/hexagon/arch.c\n@@ -199,6 +199,10 @@ void arch_fpop_start(CPUHexagonState *env)\n set_float_rounding_mode(\n softfloat_roundingmodes[fREAD_REG_FIELD(USR, USR_FPRND)],\n &env->fp_status);\n+ /*\n+ * No need to check env->hvx_fp_status, these instructions don't\n+ * raise exceptions nor interact with usr fields.\n+ */\n }\n \n #ifdef CONFIG_USER_ONLY\n@@ -232,6 +236,10 @@ void arch_fpop_end(CPUHexagonState *env, bool pkt_need_commit)\n SOFTFLOAT_TEST_FLAG(float_flag_overflow, FPOVFF, FPOVFE);\n SOFTFLOAT_TEST_FLAG(float_flag_underflow, FPUNFF, FPUNFE);\n }\n+ /*\n+ * No need to check env->hvx_fp_status, these instructions don't\n+ * raise exceptions nor interact with usr fields.\n+ */\n }\n \n int arch_sf_recip_common(float32 *Rs, float32 *Rt, float32 *Rd, int *adjust,\ndiff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c\nindex d7f4df5f96..d6ca51f175 100644\n--- a/target/hexagon/cpu.c\n+++ b/target/hexagon/cpu.c\n@@ -300,6 +300,9 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type)\n set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);\n /* Default NaN value: sign bit set, all frac bits set */\n set_float_default_nan_pattern(0b11111111, &env->fp_status);\n+\n+ set_default_nan_mode(1, &env->hvx_fp_status);\n+ set_float_default_nan_pattern(0b01111111, &env->hvx_fp_status);\n }\n \n static void hexagon_cpu_disas_set_info(const CPUState *cs,\ndiff --git a/target/hexagon/mmvec/hvx_ieee_fp.c b/target/hexagon/mmvec/hvx_ieee_fp.c\nnew file mode 100644\nindex 0000000000..3367226998\n--- /dev/null\n+++ b/target/hexagon/mmvec/hvx_ieee_fp.c\n@@ -0,0 +1,21 @@\n+/*\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"hvx_ieee_fp.h\"\n+\n+float32 fp_mult_sf_hf(float16 a1, float16 a2, float_status *fp_status)\n+{\n+ return float32_mul(float16_to_float32(a1, true, fp_status),\n+ float16_to_float32(a2, true, fp_status), fp_status);\n+}\n+\n+float32 fp_vdmpy(float16 a1, float16 a2, float16 a3, float16 a4,\n+ float_status *fp_status)\n+{\n+ return float32_add(fp_mult_sf_hf(a1, a3, fp_status),\n+ fp_mult_sf_hf(a2, a4, fp_status), fp_status);\n+}\ndiff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py\nindex 32a61505ce..9e8bcfdcf0 100755\n--- a/target/hexagon/hex_common.py\n+++ b/target/hexagon/hex_common.py\n@@ -215,6 +215,7 @@ def need_env(tag):\n \"A_LOAD\" in attribdict[tag] or\n \"A_CVI_GATHER\" in attribdict[tag] or\n \"A_CVI_SCATTER\" in attribdict[tag] or\n+ \"A_HVX_IEEE_FP\" in attribdict[tag] or\n \"A_IMPLICIT_WRITES_USR\" in attribdict[tag])\n \n \ndiff --git a/target/hexagon/imported/mmvec/encode_ext.def b/target/hexagon/imported/mmvec/encode_ext.def\nindex 6d70086b5f..4ce87d09fd 100644\n--- a/target/hexagon/imported/mmvec/encode_ext.def\n+++ b/target/hexagon/imported/mmvec/encode_ext.def\n@@ -804,5 +804,23 @@ DEF_ENC(V6_vmpyewuh, ICLASS_CJ\" 1 111 111 vvvvv PP 0 uuuuu 101 ddddd\")\n DEF_ENC(V6_vmpyowh, ICLASS_CJ\" 1 111 111 vvvvv PP 0 uuuuu 111 ddddd\")\n DEF_ENC(V6_vmpyuhvs,\"00011111110vvvvvPP1uuuuu111ddddd\")\n \n+/* IEEE FP multiply instructions */\n+DEF_ENC(V6_vmpy_sf_sf,\"00011111100vvvvvPP1uuuuu001ddddd\")\n+DEF_ENC(V6_vmpy_sf_hf,\"00011111100vvvvvPP1uuuuu010ddddd\")\n+DEF_ENC(V6_vmpy_hf_hf,\"00011111100vvvvvPP1uuuuu011ddddd\")\n+DEF_ENC(V6_vdmpy_sf_hf,\"00011111101vvvvvPP1uuuuu110ddddd\")\n+\n+/* IEEE FP multiply-accumulate instructions */\n+DEF_ENC(V6_vmpy_sf_hf_acc,\"00011100010vvvvvPP1uuuuu001xxxxx\")\n+DEF_ENC(V6_vmpy_hf_hf_acc,\"00011100010vvvvvPP1uuuuu010xxxxx\")\n+DEF_ENC(V6_vdmpy_sf_hf_acc,\"00011100010vvvvvPP1uuuuu011xxxxx\")\n+\n+/* IEEE FP add/sub instructions */\n+DEF_ENC(V6_vadd_sf_sf,\"00011111100vvvvvPP1uuuuu110ddddd\")\n+DEF_ENC(V6_vsub_sf_sf,\"00011111100vvvvvPP1uuuuu111ddddd\")\n+DEF_ENC(V6_vadd_sf_hf,\"00011111100vvvvvPP1uuuuu100ddddd\")\n+DEF_ENC(V6_vsub_sf_hf,\"00011111100vvvvvPP1uuuuu101ddddd\")\n+DEF_ENC(V6_vadd_hf_hf,\"00011111101vvvvvPP1uuuuu111ddddd\")\n+DEF_ENC(V6_vsub_hf_hf,\"00011111011vvvvvPP1uuuuu000ddddd\")\n \n #endif /* NO MMVEC */\ndiff --git a/target/hexagon/imported/mmvec/ext.idef b/target/hexagon/imported/mmvec/ext.idef\nindex 03d31f6181..14df8e4790 100644\n--- a/target/hexagon/imported/mmvec/ext.idef\n+++ b/target/hexagon/imported/mmvec/ext.idef\n@@ -2895,9 +2895,110 @@ EXTINSN(V6_vprefixqw,\"Vd32.w=prefixsum(Qv4)\", ATTRIBS(A_EXTENSION,A_CVI,A_CVI_\n }\n } )\n \n+/* KVX - IEEE FP Instructions */\n \n+/* Single pipe, 32-bit output */\n+#define ITERATOR_INSN_IEEE_FP_32(WIDTH,TAG,SYNTAX,DESCR,CODE) \\\n+EXTINSN(V6_##TAG, SYNTAX, \\\n+ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX,A_HVX_IEEE_FP_OUT_32), \\\n+DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))\n \n+/* Single pipe, 16-bit output */\n+#define ITERATOR_INSN_IEEE_FP_16(WIDTH,TAG,SYNTAX,DESCR,CODE) \\\n+EXTINSN(V6_##TAG, SYNTAX, \\\n+ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX,A_HVX_IEEE_FP_OUT_16), \\\n+DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))\n \n+/* Two pipes: P2 & P3, single output: P2, 32-bit output */\n+#define ITERATOR_INSN_IEEE_FP_DOUBLE_SINGLE_32(WIDTH,TAG,SYNTAX,DESCR,CODE) \\\n+EXTINSN(V6_##TAG, SYNTAX, \\\n+ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX_DV,A_HVX_IEEE_FP_OUT_32), \\\n+DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))\n+\n+/* Two pipes: P2 & P3, two outputs, 32-bit output */\n+#define ITERATOR_INSN_IEEE_FP_DOUBLE_32(WIDTH,TAG,SYNTAX,DESCR,CODE) \\\n+EXTINSN(V6_##TAG, SYNTAX, \\\n+ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX_DV,A_HVX_IEEE_FP_OUT_32), \\\n+DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))\n+\n+/*\n+ * single pipe, accumulate instruction, produces 16-bit output, requires 16-bit\n+ * accumulate input\n+ */\n+#define ITERATOR_INSN_IEEE_FP_ACC_16(WIDTH,TAG,SYNTAX,DESCR,CODE) \\\n+EXTINSN(V6_##TAG, SYNTAX, \\\n+ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX,A_HVX_IEEE_FP_ACC,A_HVX_IEEE_FP_OUT_16,A_CVI_VX_NO_TMP_LD), \\\n+DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))\n+\n+/*\n+ * single pipe, accumulate instruction, produces 32-bit output, requires 32-bit\n+ * accumulate input\n+ */\n+#define ITERATOR_INSN_IEEE_FP_ACC_32(WIDTH,TAG,SYNTAX,DESCR,CODE) \\\n+EXTINSN(V6_##TAG, SYNTAX, \\\n+ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX,A_HVX_IEEE_FP_ACC,A_HVX_IEEE_FP_OUT_32,A_CVI_VX_NO_TMP_LD), \\\n+DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))\n+\n+/* IEEE FP multiply instructions */\n+ITERATOR_INSN_IEEE_FP_DOUBLE_SINGLE_32(32, vmpy_sf_sf,\n+ \"Vd32.sf=vmpy(Vu32.sf,Vv32.sf)\", \"Vector IEEE mul: sf\",\n+ VdV.sf[i] = float32_mul(VuV.sf[i], VvV.sf[i], &env->hvx_fp_status))\n+ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vmpy_sf_hf,\n+ \"Vdd32.sf=vmpy(Vu32.hf,Vv32.hf)\", \"Vector IEEE mul: hf widen to sf\",\n+ VddV.v[0].sf[i] = fp_mult_sf_hf(VuV.hf[2*i], VvV.hf[2*i], &env->hvx_fp_status);\n+ VddV.v[1].sf[i] = fp_mult_sf_hf(VuV.hf[2*i+1], VvV.hf[2*i+1], &env->hvx_fp_status))\n+ITERATOR_INSN_IEEE_FP_16(16, vmpy_hf_hf, \"Vd32.hf=vmpy(Vu32.hf,Vv32.hf)\",\n+ \"Vector IEEE mul: hf\",\n+ VdV.hf[i] = float16_mul(VuV.hf[i], VvV.hf[i], &env->hvx_fp_status))\n+ITERATOR_INSN_IEEE_FP_32(32, vdmpy_sf_hf, \"Vd32.sf=vdmpy(Vu32.hf,Vv32.hf)\",\n+ \"Vector IEEE mul reduction: hf widen to sf\",\n+ VdV.sf[i] = fp_vdmpy(VuV.hf[2*i+1], VuV.hf[2*i], VvV.hf[2*i+1],\n+ VvV.hf[2*i], &env->hvx_fp_status))\n+\n+/* IEEE FP multiply-accumulate instructions */\n+ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vmpy_sf_hf_acc,\n+ \"Vxx32.sf+=vmpy(Vu32.hf,Vv32.hf)\", \"Vector IEEE fma: hf widen to sf\",\n+ VxxV.v[0].sf[i] = float32_muladd(f16_to_f32(VuV.hf[2*i]),\n+ f16_to_f32(VvV.hf[2*i]),\n+ VxxV.v[0].sf[i], 0, &env->hvx_fp_status);\n+ VxxV.v[1].sf[i] = float32_muladd(f16_to_f32(VuV.hf[2*i+1]),\n+ f16_to_f32(VvV.hf[2*i+1]),\n+ VxxV.v[1].sf[i], 0, &env->hvx_fp_status))\n+ITERATOR_INSN_IEEE_FP_ACC_16(16, vmpy_hf_hf_acc,\n+ \"Vx32.hf+=vmpy(Vu32.hf,Vv32.hf)\", \"Vector IEEE fma: hf\",\n+ VxV.hf[i] = float16_muladd(VuV.hf[i], VvV.hf[i], VxV.hf[i], 0, &env->hvx_fp_status))\n+ITERATOR_INSN_IEEE_FP_ACC_32(32, vdmpy_sf_hf_acc,\n+ \"Vx32.sf+=vdmpy(Vu32.hf,Vv32.hf)\", \"Vector IEEE fma reduce: hf widen to sf\",\n+ VxV.sf[i] = float32_add(fp_vdmpy(VuV.hf[2*i+1], VuV.hf[2*i],\n+ VvV.hf[2*i+1], VvV.hf[2*i],\n+ &env->hvx_fp_status),\n+ VxV.sf[i], &env->hvx_fp_status))\n+\n+/* IEEE FP add/sub instructions */\n+ITERATOR_INSN_IEEE_FP_32(32, vadd_sf_sf, \"Vd32.sf=vadd(Vu32.sf,Vv32.sf)\",\n+ \"Vector IEEE add: sf\",\n+ VdV.sf[i] = float32_add(VuV.sf[i], VvV.sf[i], &env->hvx_fp_status))\n+ITERATOR_INSN_IEEE_FP_32(32, vsub_sf_sf, \"Vd32.sf=vsub(Vu32.sf,Vv32.sf)\",\n+ \"Vector IEEE sub: sf\",\n+ VdV.sf[i] = float32_sub(VuV.sf[i], VvV.sf[i], &env->hvx_fp_status))\n+ITERATOR_INSN_IEEE_FP_16(16, vadd_hf_hf, \"Vd32.hf=vadd(Vu32.hf,Vv32.hf)\",\n+ \"Vector IEEE add: hf\",\n+ VdV.hf[i] = float16_add(VuV.hf[i], VvV.hf[i], &env->hvx_fp_status))\n+ITERATOR_INSN_IEEE_FP_16(16, vsub_hf_hf, \"Vd32.hf=vsub(Vu32.hf,Vv32.hf)\",\n+ \"Vector IEEE sub: hf\",\n+ VdV.hf[i] = float16_sub(VuV.hf[i], VvV.hf[i], &env->hvx_fp_status))\n+ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vadd_sf_hf,\n+ \"Vdd32.sf=vadd(Vu32.hf,Vv32.hf)\", \"Vector IEEE add: hf widen to sf\",\n+ VddV.v[0].sf[i] = float32_add(f16_to_f32(VuV.hf[2*i]),\n+ f16_to_f32(VvV.hf[2*i]), &env->hvx_fp_status);\n+ VddV.v[1].sf[i] = float32_add(f16_to_f32(VuV.hf[2*i+1]),\n+ f16_to_f32(VvV.hf[2*i+1]), &env->hvx_fp_status))\n+ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vsub_sf_hf,\n+ \"Vdd32.sf=vsub(Vu32.hf,Vv32.hf)\", \"Vector IEEE sub: hf widen to sf\",\n+ VddV.v[0].sf[i] = float32_sub(f16_to_f32(VuV.hf[2*i]),\n+ f16_to_f32(VvV.hf[2*i]), &env->hvx_fp_status);\n+ VddV.v[1].sf[i] = float32_sub(f16_to_f32(VuV.hf[2*i+1]),\n+ f16_to_f32(VvV.hf[2*i+1]), &env->hvx_fp_status))\n \n /******************************************************************************\n DEBUG Vector/Register Printing\ndiff --git a/target/hexagon/meson.build b/target/hexagon/meson.build\nindex d169cf71b2..9195014821 100644\n--- a/target/hexagon/meson.build\n+++ b/target/hexagon/meson.build\n@@ -250,6 +250,7 @@ hexagon_ss.add(files(\n 'fma_emu.c',\n 'mmvec/decode_ext_mmvec.c',\n 'mmvec/system_ext_mmvec.c',\n+ 'mmvec/hvx_ieee_fp.c',\n ))\n \n #\n","prefixes":["v3","06/16"]}