{"id":2221071,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2221071/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<2aa7f105031465bdbd63c22bca6e2b77b92bab5f.1775665981.git.matheus.bernardino@oss.qualcomm.com>","date":"2026-04-08T16:36:59","name":"[v3,08/16] target/hexagon: add v68 HVX IEEE float misc insns","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"27c61c9b9d9321b8d28c678765ce46fe409cb293","submitter":{"id":90606,"url":"http://patchwork.ozlabs.org/api/1.0/people/90606/?format=json","name":"Matheus Tavares Bernardino","email":"matheus.bernardino@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/2aa7f105031465bdbd63c22bca6e2b77b92bab5f.1775665981.git.matheus.bernardino@oss.qualcomm.com/mbox/","series":[{"id":499185,"url":"http://patchwork.ozlabs.org/api/1.0/series/499185/?format=json","date":"2026-04-08T16:36:53","name":"hexagon: add missing HVX float instructions","version":3,"mbox":"http://patchwork.ozlabs.org/series/499185/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221071/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=C+IX71Cs;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n 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autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Add HVX IEEE floating-point miscellaneous instructions:\n- vassign_fp (vfmv): vector move\n- vfneg_hf, vfneg_sf: vector floating-point negate\n- vabs_hf, vabs_sf: vector absolute value\n\nSigned-off-by: Matheus Tavares Bernardino \n---\n target/hexagon/imported/mmvec/encode_ext.def | 7 +++++++\n target/hexagon/imported/mmvec/ext.idef | 12 ++++++++++++\n 2 files changed, 19 insertions(+)","diff":"diff --git a/target/hexagon/imported/mmvec/encode_ext.def b/target/hexagon/imported/mmvec/encode_ext.def\nindex d7f50db778..72daf8724c 100644\n--- a/target/hexagon/imported/mmvec/encode_ext.def\n+++ b/target/hexagon/imported/mmvec/encode_ext.def\n@@ -833,4 +833,11 @@ DEF_ENC(V6_vmin_sf,\"00011111110vvvvvPP1uuuuu010ddddd\")\n DEF_ENC(V6_vmax_hf,\"00011111110vvvvvPP1uuuuu011ddddd\")\n DEF_ENC(V6_vmin_hf,\"00011111110vvvvvPP1uuuuu100ddddd\")\n \n+/* IEEE FP move, negate, abs instructions */\n+DEF_ENC(V6_vassign_fp,\"00011110--0-0110PP1uuuuu001ddddd\")\n+DEF_ENC(V6_vfneg_hf,\"00011110--0-0110PP1uuuuu010ddddd\")\n+DEF_ENC(V6_vfneg_sf,\"00011110--0-0110PP1uuuuu011ddddd\")\n+DEF_ENC(V6_vabs_hf,\"00011110--0-0110PP1uuuuu100ddddd\")\n+DEF_ENC(V6_vabs_sf,\"00011110--0-0110PP1uuuuu101ddddd\")\n+\n #endif /* NO MMVEC */\ndiff --git a/target/hexagon/imported/mmvec/ext.idef b/target/hexagon/imported/mmvec/ext.idef\nindex 0e9cace203..5312661684 100644\n--- a/target/hexagon/imported/mmvec/ext.idef\n+++ b/target/hexagon/imported/mmvec/ext.idef\n@@ -3034,6 +3034,18 @@ ITERATOR_INSN_ANY_SLOT_2SRC(16,vmin_hf,\"Vd32.hf=vmin(Vu32.hf,Vv32.hf)\", \\\n \"Vector min of hf input\", VdV.hf[i] = qf_min_hf(VuV.hf[i], VvV.hf[i], \\\n \t&env->hvx_fp_status))\n \n+/* IEEE FP move, negate, abs instructions */\n+ITERATOR_INSN_IEEE_FP_16_32_LATE(32, vassign_fp, \"Vd32.w=vfmv(Vu32.w)\", \\\n+ \"Vector IEEE move\", VdV.w[i] = VuV.w[i])\n+ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vfneg_hf, \"Vd32.hf=vfneg(Vu32.hf)\", \\\n+ \"Vector IEEE neg: hf\", VdV.hf[i] = float16_chs(VuV.hf[i]))\n+ITERATOR_INSN_IEEE_FP_16_32_LATE(32, vfneg_sf, \"Vd32.sf=vfneg(Vu32.sf)\", \\\n+ \"Vector IEEE neg: sf\", VdV.sf[i] = float32_chs(VuV.sf[i]))\n+ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vabs_hf, \"Vd32.hf=vabs(Vu32.hf)\", \\\n+ \"Vector IEEE abs: hf\", VdV.hf[i] = float16_abs(VuV.hf[i]))\n+ITERATOR_INSN_IEEE_FP_16_32_LATE(32, vabs_sf, \"Vd32.sf=vabs(Vu32.sf)\", \\\n+ \"Vector IEEE abs: sf\", VdV.hf[i] = float32_abs(VuV.hf[i]))\n+\n /******************************************************************************\n DEBUG Vector/Register Printing\n ******************************************************************************/\n","prefixes":["v3","08/16"]}