{"id":2219779,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2219779/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260404111318.8334E596A22@zero.eik.bme.hu>","date":"2026-04-04T11:13:18","name":"ati-vga: Fix pitch and offset registers mask","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"903327ab402135b510091ea29a92c9a7a92d4e2b","submitter":{"id":16148,"url":"http://patchwork.ozlabs.org/api/1.0/people/16148/?format=json","name":"BALATON Zoltan","email":"balaton@eik.bme.hu"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260404111318.8334E596A22@zero.eik.bme.hu/mbox/","series":[{"id":498717,"url":"http://patchwork.ozlabs.org/api/1.0/series/498717/?format=json","date":"2026-04-04T11:13:18","name":"ati-vga: Fix pitch and offset registers mask","version":1,"mbox":"http://patchwork.ozlabs.org/series/498717/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2219779/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":"legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)","Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fntJZ63vkz1xtJ\n\tfor ; Sat, 04 Apr 2026 22:14:06 +1100 (AEDT)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1w8ywU-0005jJ-9I; Sat, 04 Apr 2026 07:13:30 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1w8ywR-0005iw-BY\n for qemu-devel@nongnu.org; Sat, 04 Apr 2026 07:13:27 -0400","from zero.eik.bme.hu ([2001:738:2001:2001::2001])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1w8ywO-0005Be-ND\n for qemu-devel@nongnu.org; Sat, 04 Apr 2026 07:13:27 -0400","from localhost (localhost [127.0.0.1])\n by zero.eik.bme.hu (Postfix) with ESMTP id 93117596A24;\n Sat, 04 Apr 2026 13:13:20 +0200 (CEST)","from zero.eik.bme.hu ([127.0.0.1])\n by localhost (zero.eik.bme.hu [127.0.0.1]) (amavis, port 10028) with ESMTP\n id de0JMRN6WmMP; Sat, 4 Apr 2026 13:13:18 +0200 (CEST)","by zero.eik.bme.hu (Postfix, from userid 432)\n id 8334E596A22; Sat, 04 Apr 2026 13:13:18 +0200 (CEST)"],"X-Virus-Scanned":"amavis at eik.bme.hu","From":"BALATON Zoltan ","Subject":"[PATCH] ati-vga: Fix pitch and offset registers mask","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","To":"qemu-devel@nongnu.org","Cc":"Gerd Hoffmann , marcandre.lureau@redhat.com,\n Chad Jablonski ,\n =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ,\n Peter Maydell ","Message-Id":"<20260404111318.8334E596A22@zero.eik.bme.hu>","Date":"Sat, 04 Apr 2026 13:13:18 +0200 (CEST)","Received-SPF":"pass client-ip=2001:738:2001:2001::2001;\n envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu","X-Spam_score_int":"-18","X-Spam_score":"-1.9","X-Spam_bar":"-","X-Spam_report":"(-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Remove the Radeon specific masks for offset and pitch registers. While\nthe documentation is not clear about it I believe it is a copy&paste\nerror from the combined DST_PITCH_OFFSET register that has less bits\nso more constrained than the individual registers which should not\nhave this mask.\n\nSigned-off-by: BALATON Zoltan \n---\n hw/display/ati.c | 16 ++--------------\n 1 file changed, 2 insertions(+), 14 deletions(-)","diff":"diff --git a/hw/display/ati.c b/hw/display/ati.c\nindex 07c0961b61..5ca1912340 100644\n--- a/hw/display/ati.c\n+++ b/hw/display/ati.c\n@@ -835,18 +835,12 @@ static void ati_mm_write(void *opaque, hwaddr addr,\n ati_cursor_define(s);\n break;\n case DST_OFFSET:\n- if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {\n s->regs.dst_offset = data & 0xfffffff0;\n- } else {\n- s->regs.dst_offset = data & 0xfffffc00;\n- }\n break;\n case DST_PITCH:\n- if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {\n s->regs.dst_pitch = data & 0x3fff;\n+ if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {\n s->regs.dst_tile = (data >> 16) & 1;\n- } else {\n- s->regs.dst_pitch = data & 0x3ff0;\n }\n break;\n case DST_TILE:\n@@ -956,18 +950,12 @@ static void ati_mm_write(void *opaque, hwaddr addr,\n s->regs.dst_height = (data >> 16) & 0x3fff;\n break;\n case SRC_OFFSET:\n- if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {\n s->regs.src_offset = data & 0xfffffff0;\n- } else {\n- s->regs.src_offset = data & 0xfffffc00;\n- }\n break;\n case SRC_PITCH:\n- if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {\n s->regs.src_pitch = data & 0x3fff;\n+ if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {\n s->regs.src_tile = (data >> 16) & 1;\n- } else {\n- s->regs.src_pitch = data & 0x3ff0;\n }\n break;\n case DP_BRUSH_BKGD_CLR:\n","prefixes":[]}