{"id":2219471,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2219471/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260403035541.18355-14-zhenzhong.duan@intel.com>","date":"2026-04-03T03:55:37","name":"[v3,13/14] intel_iommu_accel: Add pasid bits size check","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"da795dbc0966595dd77cfbca90faddadc7785654","submitter":{"id":81636,"url":"http://patchwork.ozlabs.org/api/1.0/people/81636/?format=json","name":"Duan, Zhenzhong","email":"zhenzhong.duan@intel.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260403035541.18355-14-zhenzhong.duan@intel.com/mbox/","series":[{"id":498583,"url":"http://patchwork.ozlabs.org/api/1.0/series/498583/?format=json","date":"2026-04-03T03:55:36","name":"intel_iommu: Enable PASID support for passthrough device","version":3,"mbox":"http://patchwork.ozlabs.org/series/498583/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2219471/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=LdGwZktx;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Thu, 02 Apr 2026 23:56:39 -0400","from fmviesa007.fm.intel.com ([10.60.135.147])\n by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 02 Apr 2026 20:56:37 -0700","from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229])\n by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 02 Apr 2026 20:56:34 -0700"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1775188598; x=1806724598;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=hIU2vlg7EXU+6k1wCa3nxm6yYsN20b7avvilirDWblw=;\n b=LdGwZktxbfBn00JVP3m59qPlDVNWd0/P3xdDrcAK+4bAmKb+K3+Bx7LA\n gPXy3vSVp+fo7NffmX+Zp6Ub4OPmvEM93RbX4d9m9VF6+Z72VEXHLEoPy\n ohtI76dT+EYjrEqpfAIiD3Nc+uietlRPGdjrKqtueRZUTCby6cjklUjuu\n 2Kf1kp+gqBiB7xQbONW+4ICnDy/s/VlvZ3TT0/icEligWnLSnuBT6jDkA\n piE4E7Hjhsnago2y5ql1tKRNnnPhUbHg5wlgUQj2bDwNQCwjOruAbz3fs\n Au/0C1U8VGcS6hi13MGF+WuzY7LpJAbs1BCJdoV3fMiW8NbR2kHfp9YDb g==;","X-CSE-ConnectionGUID":["ph6NiwdIR42qUxhG3A4gbg==","uvjp4ho6TNKSUu1bvxSIgQ=="],"X-CSE-MsgGUID":["0JMh05t5TBWDSdZwjfi64Q==","R5YnfWPvQZ+OEeByqwm1GA=="],"X-IronPort-AV":["E=McAfee;i=\"6800,10657,11747\"; a=\"76140693\"","E=Sophos;i=\"6.23,157,1770624000\"; d=\"scan'208\";a=\"76140693\"","E=Sophos;i=\"6.23,157,1770624000\"; d=\"scan'208\";a=\"223884952\""],"X-ExtLoop1":"1","From":"Zhenzhong Duan ","To":"qemu-devel@nongnu.org","Cc":"alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com,\n jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com,\n skolothumtho@nvidia.com, joao.m.martins@oracle.com,\n clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com,\n xudong.hao@intel.com, Zhenzhong Duan ","Subject":"[PATCH v3 13/14] intel_iommu_accel: Add pasid bits size check","Date":"Thu, 2 Apr 2026 23:55:37 -0400","Message-ID":"<20260403035541.18355-14-zhenzhong.duan@intel.com>","X-Mailer":"git-send-email 2.47.3","In-Reply-To":"<20260403035541.18355-1-zhenzhong.duan@intel.com>","References":"<20260403035541.18355-1-zhenzhong.duan@intel.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=198.175.65.19;\n envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com","X-Spam_score_int":"-48","X-Spam_score":"-4.9","X-Spam_bar":"----","X-Spam_report":"(-4.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.542,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"If pasid bits size is bigger than host side, host could fail to emulate\nall bindings in guest. Add a check to fail device plug early.\n\nSigned-off-by: Zhenzhong Duan \nTested-by: Xudong Hao \n---\n hw/i386/intel_iommu_internal.h | 1 +\n hw/i386/intel_iommu_accel.c | 8 ++++++++\n 2 files changed, 9 insertions(+)","diff":"diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h\nindex 2c716c5297..519af3fa90 100644\n--- a/hw/i386/intel_iommu_internal.h\n+++ b/hw/i386/intel_iommu_internal.h\n@@ -196,6 +196,7 @@\n #define VTD_ECAP_SRS (1ULL << 31)\n #define VTD_ECAP_NWFS (1ULL << 33)\n #define VTD_ECAP_SET_PSS(x, v) ((x)->ecap = deposit64((x)->ecap, 35, 5, v))\n+#define VTD_ECAP_GET_PSS(ecap) extract64(ecap, 35, 5)\n #define VTD_ECAP_PASID (1ULL << 40)\n #define VTD_ECAP_PDS (1ULL << 42)\n #define VTD_ECAP_SMTS (1ULL << 43)\ndiff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c\nindex 6377db1fb9..32e2c4633f 100644\n--- a/hw/i386/intel_iommu_accel.c\n+++ b/hw/i386/intel_iommu_accel.c\n@@ -44,6 +44,7 @@ bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod,\n HostIOMMUDevice *hiod = vtd_hiod->hiod;\n struct HostIOMMUDeviceCaps *caps = &hiod->caps;\n struct iommu_hw_info_vtd *vtd = &caps->vendor_caps.vtd;\n+ uint8_t hpasid = VTD_ECAP_GET_PSS(vtd->ecap_reg) + 1;\n PCIBus *bus = vtd_hiod->bus;\n PCIDevice *pdev = bus->devices[vtd_hiod->devfn];\n \n@@ -64,6 +65,13 @@ bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod,\n return false;\n }\n \n+ /* Only do the check when host device support PASIDs */\n+ if (caps->max_pasid_log2 && s->pasid > hpasid) {\n+ error_setg(errp, \"PASID bits size %d > host IOMMU PASID bits size %d\",\n+ s->pasid, hpasid);\n+ return false;\n+ }\n+\n if (pci_device_get_iommu_bus_devfn(pdev, &bus, NULL, NULL)) {\n error_setg(errp, \"Host device downstream to a PCI bridge is \"\n \"unsupported when x-flts=on\");\n","prefixes":["v3","13/14"]}