{"id":2219470,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2219470/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260403035541.18355-15-zhenzhong.duan@intel.com>","date":"2026-04-03T03:55:38","name":"[v3,14/14] intel_iommu: Expose flag VIOMMU_FLAG_PASID_SUPPORTED when configured","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"524e9c92d1c50e0a3a5e718f65994257170df937","submitter":{"id":81636,"url":"http://patchwork.ozlabs.org/api/1.0/people/81636/?format=json","name":"Duan, Zhenzhong","email":"zhenzhong.duan@intel.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260403035541.18355-15-zhenzhong.duan@intel.com/mbox/","series":[{"id":498583,"url":"http://patchwork.ozlabs.org/api/1.0/series/498583/?format=json","date":"2026-04-03T03:55:36","name":"intel_iommu: Enable PASID support for passthrough device","version":3,"mbox":"http://patchwork.ozlabs.org/series/498583/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2219470/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=iMdWPuMM;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=\"76140700\"","E=Sophos;i=\"6.23,157,1770624000\"; d=\"scan'208\";a=\"76140700\"","E=Sophos;i=\"6.23,157,1770624000\"; d=\"scan'208\";a=\"223884968\""],"X-ExtLoop1":"1","From":"Zhenzhong Duan ","To":"qemu-devel@nongnu.org","Cc":"alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com,\n jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com,\n skolothumtho@nvidia.com, joao.m.martins@oracle.com,\n clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com,\n xudong.hao@intel.com, Zhenzhong Duan ","Subject":"[PATCH v3 14/14] intel_iommu: Expose flag VIOMMU_FLAG_PASID_SUPPORTED\n when configured","Date":"Thu, 2 Apr 2026 23:55:38 -0400","Message-ID":"<20260403035541.18355-15-zhenzhong.duan@intel.com>","X-Mailer":"git-send-email 2.47.3","In-Reply-To":"<20260403035541.18355-1-zhenzhong.duan@intel.com>","References":"<20260403035541.18355-1-zhenzhong.duan@intel.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=198.175.65.19;\n envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com","X-Spam_score_int":"-48","X-Spam_score":"-4.9","X-Spam_bar":"----","X-Spam_report":"(-4.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.542,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"VFIO device will check flag VIOMMU_FLAG_PASID_SUPPORTED and expose PASID\ncapability, or else guest could not enable PASID of this device even if\nvIOMMU's pasid is configured.\n\nThis is the final knob to enable PASID.\n\nSigned-off-by: Zhenzhong Duan \nTested-by: Xudong Hao \n---\n hw/i386/intel_iommu.c | 1 +\n 1 file changed, 1 insertion(+)","diff":"diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c\nindex abcb0df5d9..3cb8a547c7 100644\n--- a/hw/i386/intel_iommu.c\n+++ b/hw/i386/intel_iommu.c\n@@ -4794,6 +4794,7 @@ static uint64_t vtd_get_viommu_flags(void *opaque)\n uint64_t flags;\n \n flags = s->fsts ? VIOMMU_FLAG_WANT_NESTING_PARENT : 0;\n+ flags |= s->pasid ? VIOMMU_FLAG_PASID_SUPPORTED : 0;\n \n return flags;\n }\n","prefixes":["v3","14/14"]}