{"id":2219238,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2219238/?format=json","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/1.0/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260402163840.938417-3-shubhrajyoti.datta@amd.com>","date":"2026-04-02T16:38:40","name":"[2/2] gpio: zynq: Add eio gpio support","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"cf72db7257d349ce96afe6a7a67ddbf24ce9e1fa","submitter":{"id":84267,"url":"http://patchwork.ozlabs.org/api/1.0/people/84267/?format=json","name":"Shubhrajyoti Datta","email":"shubhrajyoti.datta@amd.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260402163840.938417-3-shubhrajyoti.datta@amd.com/mbox/","series":[{"id":498511,"url":"http://patchwork.ozlabs.org/api/1.0/series/498511/?format=json","date":"2026-04-02T16:38:40","name":"gpio: Add EIO GPIO support","version":1,"mbox":"http://patchwork.ozlabs.org/series/498511/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2219238/checks/","tags":{},"headers":{"Return-Path":"\n <linux-gpio+bounces-34602-incoming=patchwork.ozlabs.org@vger.kernel.org>","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=amd.com header.i=@amd.com header.a=rsa-sha256\n header.s=selector1 header.b=GUXjHd8i;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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helo=satlexmb08.amd.com; pr=C","From":"Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>","To":"<linux-kernel@vger.kernel.org>","CC":"<git@amd.com>, <shubhrajyoti.datta@gmail.com>, Shubhrajyoti Datta\n\t<shubhrajyoti.datta@amd.com>, Srinivas Neeli <srinivas.neeli@amd.com>,\n\t\"Michal Simek\" <michal.simek@amd.com>, Linus Walleij <linusw@kernel.org>,\n\t\"Bartosz Golaszewski\" <brgl@kernel.org>, Rob Herring <robh@kernel.org>,\n\t\"Krzysztof Kozlowski\" <krzk+dt@kernel.org>, Conor Dooley\n\t<conor+dt@kernel.org>, <linux-gpio@vger.kernel.org>,\n\t<devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>","Subject":"[PATCH 2/2] gpio: zynq: Add eio gpio support","Date":"Thu, 2 Apr 2026 22:08:40 +0530","Message-ID":"<20260402163840.938417-3-shubhrajyoti.datta@amd.com>","X-Mailer":"git-send-email 2.34.1","In-Reply-To":"<20260402163840.938417-1-shubhrajyoti.datta@amd.com>","References":"<20260402163840.938417-1-shubhrajyoti.datta@amd.com>","Precedence":"bulk","X-Mailing-List":"linux-gpio@vger.kernel.org","List-Id":"<linux-gpio.vger.kernel.org>","List-Subscribe":"<mailto:linux-gpio+subscribe@vger.kernel.org>","List-Unsubscribe":"<mailto:linux-gpio+unsubscribe@vger.kernel.org>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-EOPAttributedMessage":"0","X-MS-PublicTrafficType":"Email","X-MS-TrafficTypeDiagnostic":"DS3PEPF0000C37B:EE_|PH0PR12MB8174:EE_","X-MS-Office365-Filtering-Correlation-Id":"35439377-9ea7-4316-4a38-08de90d656a8","X-MS-Exchange-SenderADCheck":"1","X-MS-Exchange-AntiSpam-Relay":"0","X-Microsoft-Antispam":"\n\tBCL:0;ARA:13230040|7416014|376014|82310400026|36860700016|1800799024|18002099003|56012099003|22082099003;","X-Microsoft-Antispam-Message-Info":"\n\tk1Hb+xK34T145NCSKY8oCf/mCzSBAwYOSsr82Yic3LR8dJwe/3Upoio3peKW2IVsmSH07sQASnYdTw7Tr2mirdx/BV0x+Ev3YrRrqpkBlacCJ6BAmzDFz76RXRt/2/h20a1ifB006rHvOSiEyCuYDiqkR9MdpdDZCfkiC79VmpsQM3qyon9d+8o2GWtSDUCL3sg1O6mAiPLyX20u1MLKJXCc4Sxw7paOT5Mw1QDBXmgcX3I/OAiXuxK3OmJeAIo+hF0YdpGsaTExocssJcuxMUvvtWQv1mstgwePBFA8wDV4xTv7hIIAToc5BFuAUy/FoR5plMtybHPLlVBiZXNqSDm3l5LMIJNTckv72dwv4p5JgwI08A1wHKBWGrpL2zZSa3hy/cBhvFFtcDieehM2w9cblIqHBpMvnLfKcIwPZyujlCgTZTdS/hsRR035+SONxUgttBEH/X25OccFryjVdiaeMBHtMkXA56WF5qNt3ui7v5ODuli+NlBj/AvvfPMHm/fhbyKofxgB02pKbnxt9lu5mItWkunlpgM3aLBazG1ux9lDJTaBpL9/26n8tXFJweircK1sLwalA+acnJ3ADk8+u9HojfqkVyOs3vtxtsVUi08aMsyAp3sY6Y8fgOEgkb7U0a+vm/CQ4oqIDw4181Upo4WcEwKJjpTQOwYkA18I1FLAsMbl3gesUmRawvWESMfWG9DT5UjKwwIW2GXFdOW6bKrI7E+qOMn9FasSSQTR7YHcgE7ZsuyfQ9oH51WI8JlF18r4fs520QgzNu6q6w==","X-Forefront-Antispam-Report":"\n\tCIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(7416014)(376014)(82310400026)(36860700016)(1800799024)(18002099003)(56012099003)(22082099003);DIR:OUT;SFP:1101;","X-MS-Exchange-AntiSpam-MessageData-ChunkCount":"1","X-MS-Exchange-AntiSpam-MessageData-0":"\n\tPp4iS+5bFceeAUL1cwR78qvzS30TJTn0GXczzuU6ayeqgKaV9ZGwiidltC910w1n+d7DMlirpQg3OH4VCrp9NuY6CHBPXieGLCWY7P5fL/en/tJOSfkOyiNiTNasSQF4hOfpvTun/e+NE0d+Ixo/WVdHilJQKhKgta9tPqeNcjmaM2ewZcrXIVwkM8zUdcSlmrykn2V+r1QGwqaY/Xp4+xT093tnm0M4CFzqwv/vw159AcoPau3+PAZPRn64EWJVwsBXiikHACWjhypj2xLd2zqef66BrtM5DJYDijq3wOGPi0eX53kqQhGNSXLX0UqFY568sPowvKhdT/fHAWKZiAfU2S3e1scLtdVlGEcwlcvpQBE0LvSYBtQ+5ns4lKywDPRo+7yj73ziMzgAMW7ROjyucXbLBI2I1hVEVNiDhSvb2DdmFf9dBDkG00h5Q/hc","X-OriginatorOrg":"amd.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"02 Apr 2026 16:38:58.4042\n (UTC)","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 35439377-9ea7-4316-4a38-08de90d656a8","X-MS-Exchange-CrossTenant-Id":"3dd8961f-e488-4e60-8e11-a82d994e183d","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n\tDS3PEPF0000C37B.namprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"PH0PR12MB8174"},"content":"Add support for the EIO GPIO controller found on\nxa2ve3288 silicon.\n\nThe EIO GPIO block provides access to multiplexed I/O pins exposed\nthrough the EIO interface. Only bank 0 and bank 1 are connected to\nexternal MIO pins, with 26 GPIOs per bank (52 GPIOs total). This\nchange extends the Zynq GPIO driver to support the EIO GPIO\nvariant.\n\nSigned-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>\n---\n\n drivers/gpio/gpio-zynq.c | 12 ++++++++++++\n 1 file changed, 12 insertions(+)","diff":"diff --git a/drivers/gpio/gpio-zynq.c b/drivers/gpio/gpio-zynq.c\nindex 571e366624d2..8118ae3412c2 100644\n--- a/drivers/gpio/gpio-zynq.c\n+++ b/drivers/gpio/gpio-zynq.c\n@@ -25,6 +25,7 @@\n #define VERSAL_GPIO_MAX_BANK\t4\n #define PMC_GPIO_MAX_BANK\t5\n #define VERSAL_UNUSED_BANKS\t2\n+#define EIO_GPIO_MAX_BANK\t2\n \n #define ZYNQ_GPIO_BANK0_NGPIO\t32\n #define ZYNQ_GPIO_BANK1_NGPIO\t22\n@@ -818,6 +819,16 @@ static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {\n \tRUNTIME_PM_OPS(zynq_gpio_runtime_suspend, zynq_gpio_runtime_resume, NULL)\n };\n \n+static const struct zynq_platform_data eio_gpio_def = {\n+\t.label = \"eio_gpio\",\n+\t.ngpio = 52,\n+\t.max_bank = EIO_GPIO_MAX_BANK,\n+\t.bank_min[0] = 0,\n+\t.bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */\n+\t.bank_min[1] = 26,\n+\t.bank_max[1] = 51, /* Bank 1 are connected to MIOs (26 pins) */\n+};\n+\n static const struct zynq_platform_data versal_gpio_def = {\n \t.label = \"versal_gpio\",\n \t.quirks = GPIO_QUIRK_VERSAL,\n@@ -882,6 +893,7 @@ static const struct of_device_id zynq_gpio_of_match[] = {\n \t{ .compatible = \"xlnx,zynqmp-gpio-1.0\", .data = &zynqmp_gpio_def },\n \t{ .compatible = \"xlnx,versal-gpio-1.0\", .data = &versal_gpio_def },\n \t{ .compatible = \"xlnx,pmc-gpio-1.0\", .data = &pmc_gpio_def },\n+\t{ .compatible = \"xlnx,eio-gpio-1.0\", .data = &eio_gpio_def },\n \t{ /* end of table */ }\n };\n MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);\n","prefixes":["2/2"]}