{"id":2219193,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2219193/?format=json","project":{"id":21,"url":"http://patchwork.ozlabs.org/api/1.0/projects/21/?format=json","name":"Linux Tegra Development","link_name":"linux-tegra","list_id":"linux-tegra.vger.kernel.org","list_email":"linux-tegra@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260402-tegra264-pcie-v4-2-21e2e19987e8@nvidia.com>","date":"2026-04-02T14:27:36","name":"[v4,2/4] PCI: Use standard wait times for PCIe link monitoring","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"c718764f791e6c54805fd259ecbc2fb39608a7fd","submitter":{"id":92481,"url":"http://patchwork.ozlabs.org/api/1.0/people/92481/?format=json","name":"Thierry Reding","email":"thierry.reding@kernel.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260402-tegra264-pcie-v4-2-21e2e19987e8@nvidia.com/mbox/","series":[{"id":498493,"url":"http://patchwork.ozlabs.org/api/1.0/series/498493/?format=json","date":"2026-04-02T14:27:35","name":"PCI: tegra: Add Tegra264 support","version":4,"mbox":"http://patchwork.ozlabs.org/series/498493/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2219193/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=FdmBp7yZ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; 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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260402-tegra264-pcie-v4-2-21e2e19987e8@nvidia.com>","References":"<20260402-tegra264-pcie-v4-0-21e2e19987e8@nvidia.com>","In-Reply-To":"<20260402-tegra264-pcie-v4-0-21e2e19987e8@nvidia.com>","To":"Bjorn Helgaas ,\n Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?=\n\t=?utf-8?q?=C5=84ski?= ,\n Manivannan Sadhasivam , Rob Herring ,\n Krzysztof Kozlowski ,\n Conor Dooley ,\n Thierry Reding ,\n Jonathan Hunter ,\n Karthikeyan Mitran ,\n Hou Zhiqiang ,\n Thomas Petazzoni ,\n =?utf-8?q?Pali_Roh=C3=A1r?= ,\n Michal Simek , Kevin Xie ","Cc":"linux-pci@vger.kernel.org, devicetree@vger.kernel.org,\n linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,\n linux-arm-kernel@lists.infradead.org, Thierry Reding ","X-Mailer":"b4 0.15.1","X-Developer-Signature":"v=1; a=openpgp-sha256; l=7887; i=treding@nvidia.com;\n h=from:subject:message-id; bh=oVBJHFwB+gdNI7W/8nXEvJ4Aw93e6oLvRNS3XbChGUY=;\n b=owEBbQKS/ZANAwAKAd0jrNd/PrOhAcsmYgBpznzo0GCVjwX6st8+h0v682ZUEPkxIqGzROXu5\n Nfbq+SWm8GJAjMEAAEKAB0WIQSI6sMIAUnM98CNyJ/dI6zXfz6zoQUCac586AAKCRDdI6zXfz6z\n oWyWD/9KqFx3AWLsen71eImhEUWi5Vbr2EBrypY2+xZH9iKEKVVlJX6zH8ICwWXLq/9S1CoF7BI\n gyYELvWzJEiM6ESCDHKhPNtvGAoFCET+VjruIN+kzkv3g9g0n3yijseZDE3XYLW2n+fCQgrc/ue\n gv7U+JfI6npA9oOfh3rsk9jciSVRay4VjYG+IzF7kvWZFsIhDS1ComrThVZMJVXgYFHJ/EMm/1J\n uSZ2vSSneNVSp637VzbNkj4uxxHJBj9TZ81Qq3faJk7BNQOrSKbcJfZzbffZYxDYLBesi8fwKny\n oRsfmO86HYyG18GpqzHW4l3UEU+1EkO3H6Z0BN0j4rX1ZAGhe/RtzbZcoQBhvyla3/5OotxSGWp\n 1zlZCz//YAA3VgdBTNI3ob5gd+3rQI6tXRCuRiO1zWmr9z/LBsOOJf47m7Fkcbm9vomT59v1azx\n XRgTCgolqoI1+LSMXlS7/hF8VU4otMyvnROWai7BSFtLOOKgUU7nuF74TwbSCTo9IYbVJkNR3n8\n serEUq/fObYix+yblw+nJqup+1zMA1nRuEa6KAU+7VqR//N/0kC8N7jx+0LXv67NjShXyH1UxCz\n cyxfUhS7mCo/PdAMIw7ttGQOksFOKFNN1cGiYY8IOqqDHc0ljMdVuOC4PY2DYYgAgwXgaFrLxOo\n drF5PgjYPbDmGyA==","X-Developer-Key":"i=treding@nvidia.com; a=openpgp;\n fpr=88EAC3080149CCF7C08DC89FDD23ACD77F3EB3A1"},"content":"From: Thierry Reding \n\nInstead of defining the wait values for each driver, use common values\ndefined in the core pci.h header file. Note that most drivers don't use\nthe millisecond waits, but rather usleep_range(), so add these commonly\nused values to the header so that all drivers can use them.\n\nSigned-off-by: Thierry Reding \n---\nChanges in v2:\n- fix build for Cadence\n---\n drivers/pci/controller/cadence/pcie-cadence-host-common.c | 6 ++++--\n drivers/pci/controller/cadence/pcie-cadence-lga-regs.h | 5 -----\n drivers/pci/controller/mobiveil/pcie-mobiveil.c | 4 ++--\n drivers/pci/controller/mobiveil/pcie-mobiveil.h | 5 -----\n drivers/pci/controller/pci-aardvark.c | 7 ++-----\n drivers/pci/controller/pcie-xilinx-nwl.c | 9 ++-------\n drivers/pci/controller/plda/pcie-starfive.c | 9 ++-------\n drivers/pci/pci.h | 2 ++\n 8 files changed, 14 insertions(+), 33 deletions(-)","diff":"diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.c b/drivers/pci/controller/cadence/pcie-cadence-host-common.c\nindex 2b0211870f02..72b36c70f389 100644\n--- a/drivers/pci/controller/cadence/pcie-cadence-host-common.c\n+++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.c\n@@ -15,6 +15,8 @@\n #include \"pcie-cadence.h\"\n #include \"pcie-cadence-host-common.h\"\n \n+#include \"../../pci.h\"\n+\n #define LINK_RETRAIN_TIMEOUT HZ\n \n u64 bar_max_size[] = {\n@@ -53,12 +55,12 @@ int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie,\n \tint retries;\n \n \t/* Check if the link is up or not */\n-\tfor (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {\n+\tfor (retries = 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) {\n \t\tif (pcie_link_up(pcie)) {\n \t\t\tdev_info(dev, \"Link up\\n\");\n \t\t\treturn 0;\n \t\t}\n-\t\tusleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);\n+\t\tusleep_range(PCIE_LINK_WAIT_US_MIN, PCIE_LINK_WAIT_US_MAX);\n \t}\n \n \treturn -ETIMEDOUT;\ndiff --git a/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h b/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h\nindex 857b2140c5d2..15dc4fcaf45d 100644\n--- a/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h\n+++ b/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h\n@@ -10,11 +10,6 @@\n \n #include \n \n-/* Parameters for the waiting for link up routine */\n-#define LINK_WAIT_MAX_RETRIES\t10\n-#define LINK_WAIT_USLEEP_MIN\t90000\n-#define LINK_WAIT_USLEEP_MAX\t100000\n-\n /* Local Management Registers */\n #define CDNS_PCIE_LM_BASE\t0x00100000\n \ndiff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.c b/drivers/pci/controller/mobiveil/pcie-mobiveil.c\nindex 62ecbaeb0a60..cc102032c1e6 100644\n--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.c\n+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.c\n@@ -218,11 +218,11 @@ int mobiveil_bringup_link(struct mobiveil_pcie *pcie)\n \tint retries;\n \n \t/* check if the link is up or not */\n-\tfor (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {\n+\tfor (retries = 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) {\n \t\tif (mobiveil_pcie_link_up(pcie))\n \t\t\treturn 0;\n \n-\t\tusleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);\n+\t\tusleep_range(PCIE_LINK_WAIT_US_MIN, PCIE_LINK_WAIT_US_MAX);\n \t}\n \n \tdev_err(&pcie->pdev->dev, \"link never came up\\n\");\ndiff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h\nindex 7246de6a7176..11010a99e27c 100644\n--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h\n+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h\n@@ -122,11 +122,6 @@\n #define IB_WIN_SIZE\t\t\t((u64)256 * 1024 * 1024 * 1024)\n #define MAX_PIO_WINDOWS\t\t\t8\n \n-/* Parameters for the waiting for link up routine */\n-#define LINK_WAIT_MAX_RETRIES\t\t10\n-#define LINK_WAIT_MIN\t\t\t90000\n-#define LINK_WAIT_MAX\t\t\t100000\n-\n #define PAGED_ADDR_BNDRY\t\t0xc00\n #define OFFSET_TO_PAGE_ADDR(off)\t\\\n \t((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY)\ndiff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c\nindex e34bea1ff0ac..506323a6c72b 100644\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -255,9 +255,6 @@ enum {\n #define PIO_RETRY_CNT\t\t\t750000 /* 1.5 s */\n #define PIO_RETRY_DELAY\t\t\t2 /* 2 us*/\n \n-#define LINK_WAIT_MAX_RETRIES\t\t10\n-#define LINK_WAIT_USLEEP_MIN\t\t90000\n-#define LINK_WAIT_USLEEP_MAX\t\t100000\n #define RETRAIN_WAIT_MAX_RETRIES\t10\n #define RETRAIN_WAIT_USLEEP_US\t\t2000\n \n@@ -349,11 +346,11 @@ static int advk_pcie_wait_for_link(struct advk_pcie *pcie)\n \tint retries;\n \n \t/* check if the link is up or not */\n-\tfor (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {\n+\tfor (retries = 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) {\n \t\tif (advk_pcie_link_up(pcie))\n \t\t\treturn 0;\n \n-\t\tusleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);\n+\t\tusleep_range(PCIE_LINK_WAIT_US_MIN, PCIE_LINK_WAIT_US_MAX);\n \t}\n \n \treturn -ETIMEDOUT;\ndiff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c\nindex 7db2c96c6cec..fc65e9fdddb3 100644\n--- a/drivers/pci/controller/pcie-xilinx-nwl.c\n+++ b/drivers/pci/controller/pcie-xilinx-nwl.c\n@@ -140,11 +140,6 @@\n #define PCIE_PHY_LINKUP_BIT\t\tBIT(0)\n #define PHY_RDY_LINKUP_BIT\t\tBIT(1)\n \n-/* Parameters for the waiting for link up routine */\n-#define LINK_WAIT_MAX_RETRIES 10\n-#define LINK_WAIT_USLEEP_MIN 90000\n-#define LINK_WAIT_USLEEP_MAX 100000\n-\n struct nwl_msi {\t\t\t/* MSI information */\n \tDECLARE_BITMAP(bitmap, INT_PCI_MSI_NR);\n \tstruct irq_domain *dev_domain;\n@@ -203,10 +198,10 @@ static int nwl_wait_for_link(struct nwl_pcie *pcie)\n \tint retries;\n \n \t/* check if the link is up or not */\n-\tfor (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {\n+\tfor (retries = 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) {\n \t\tif (nwl_phy_link_up(pcie))\n \t\t\treturn 0;\n-\t\tusleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);\n+\t\tusleep_range(PCIE_LINK_WAIT_US_MIN, PCIE_LINK_WAIT_US_MAX);\n \t}\n \n \tdev_err(dev, \"PHY link never came up\\n\");\ndiff --git a/drivers/pci/controller/plda/pcie-starfive.c b/drivers/pci/controller/plda/pcie-starfive.c\nindex 298036c3e7f9..542a751b6f4d 100644\n--- a/drivers/pci/controller/plda/pcie-starfive.c\n+++ b/drivers/pci/controller/plda/pcie-starfive.c\n@@ -45,11 +45,6 @@\n #define STG_SYSCON_LNKSTA_OFFSET\t\t0x170\n #define DATA_LINK_ACTIVE\t\t\tBIT(5)\n \n-/* Parameters for the waiting for link up routine */\n-#define LINK_WAIT_MAX_RETRIES\t10\n-#define LINK_WAIT_USLEEP_MIN\t90000\n-#define LINK_WAIT_USLEEP_MAX\t100000\n-\n struct starfive_jh7110_pcie {\n \tstruct plda_pcie_rp plda;\n \tstruct reset_control *resets;\n@@ -217,12 +212,12 @@ static int starfive_pcie_host_wait_for_link(struct starfive_jh7110_pcie *pcie)\n \tint retries;\n \n \t/* Check if the link is up or not */\n-\tfor (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {\n+\tfor (retries = 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) {\n \t\tif (starfive_pcie_link_up(&pcie->plda)) {\n \t\t\tdev_info(pcie->plda.dev, \"port link up\\n\");\n \t\t\treturn 0;\n \t\t}\n-\t\tusleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);\n+\t\tusleep_range(PCIE_LINK_WAIT_US_MIN, PCIE_LINK_WAIT_US_MAX);\n \t}\n \n \treturn -ETIMEDOUT;\ndiff --git a/drivers/pci/pci.h b/drivers/pci/pci.h\nindex 13d998fbacce..f47ed96d8ef2 100644\n--- a/drivers/pci/pci.h\n+++ b/drivers/pci/pci.h\n@@ -63,6 +63,8 @@ struct pcie_tlp_log;\n /* Parameters for the waiting for link up routine */\n #define PCIE_LINK_WAIT_MAX_RETRIES\t10\n #define PCIE_LINK_WAIT_SLEEP_MS\t\t90\n+#define PCIE_LINK_WAIT_US_MIN\t\t90000\n+#define PCIE_LINK_WAIT_US_MAX\t\t100000\n \n /* Format of TLP; PCIe r7.0, sec 2.2.1 */\n #define PCIE_TLP_FMT_3DW_NO_DATA\t0x00 /* 3DW header, no data */\n","prefixes":["v4","2/4"]}