{"id":2219159,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2219159/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260402-mshv_accel_arm64_supp-v2-7-754895c15e9e@linux.microsoft.com>","date":"2026-04-02T12:52:34","name":"[v2,07/14] accel/mshv: Add access_vp_regs synthetic proc features","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"a6b141731bd78f8e674069a1aa85931572663061","submitter":{"id":92925,"url":"http://patchwork.ozlabs.org/api/1.0/people/92925/?format=json","name":"Aastha Rawat","email":"aastharawat@linux.microsoft.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260402-mshv_accel_arm64_supp-v2-7-754895c15e9e@linux.microsoft.com/mbox/","series":[{"id":498484,"url":"http://patchwork.ozlabs.org/api/1.0/series/498484/?format=json","date":"2026-04-02T12:52:39","name":"Add ARM64 support for MSHV accelerator","version":2,"mbox":"http://patchwork.ozlabs.org/series/498484/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2219159/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.microsoft.com header.i=@linux.microsoft.com\n header.a=rsa-sha256 header.s=default header.b=Lq4cV0fh;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n s=default; t=1775134383;\n bh=aiVWl92e6PUYoJGvSxfSYd8qlj5urawU2dcb1f8iQJs=;\n h=From:Date:Subject:References:In-Reply-To:To:Cc:From;\n b=Lq4cV0fhYzNvugDB2XCRbqpYKCEsHsmwjbe9/Bi8Db/u7sVWDjEtAkTF1YpcGF+GT\n MS5CNdgaj/6PYruCoGHwjWktVP/N2LSRh+Ny0o/+AXk9tvOuET3Pv6nJLavbeir9tT\n JSqnx2cedcVs06Gsdzn3VSQV7P5sfSQBcXzaVWOM=","From":"Aastha Rawat ","Date":"Thu, 02 Apr 2026 12:52:34 +0000","Subject":"[PATCH v2 07/14] accel/mshv: Add access_vp_regs synthetic proc\n features","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"\n <20260402-mshv_accel_arm64_supp-v2-7-754895c15e9e@linux.microsoft.com>","References":"\n <20260402-mshv_accel_arm64_supp-v2-0-754895c15e9e@linux.microsoft.com>","In-Reply-To":"\n <20260402-mshv_accel_arm64_supp-v2-0-754895c15e9e@linux.microsoft.com>","To":"qemu-devel@nongnu.org","Cc":"Magnus Kulke ,\n Wei Liu , Paolo Bonzini ,\n\t=?utf-8?q?Marc-Andr=C3=A9_Lureau?= ,\n\t=?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , =?utf-8?q?Phil?=\n\t=?utf-8?q?ippe_Mathieu-Daud=C3=A9?= ,\n Peter Maydell ,\n Anirudh Rayabharam ,\n Aastha Rawat ,\n Magnus Kulke , qemu-arm@nongnu.org,\n Alexander Graf , Pedro Barbuda ,\n Mohamed Mediouni ","X-Mailer":"b4 0.15.1","Received-SPF":"pass client-ip=13.77.154.182;\n envelope-from=aastharawat@linux.microsoft.com; helo=linux.microsoft.com","X-Spam_score_int":"-42","X-Spam_score":"-4.3","X-Spam_bar":"----","X-Spam_report":"(-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Enable access_vp_regs feature for regs. In arm64, this feature bit\nallows the guest to set VP registers using hypercall. This wasn't\nrequired for x86 because such registers are set using wrmsr instead of\nhypercall.\n\nSigned-off-by: Aastha Rawat \n---\n accel/mshv/mshv-all.c | 1 +\n include/hw/hyperv/hvhdk.h | 91 ++++++++++++++++++++++++++++++++++++++++++++++-\n 2 files changed, 91 insertions(+), 1 deletion(-)","diff":"diff --git a/accel/mshv/mshv-all.c b/accel/mshv/mshv-all.c\nindex 6940ad9989..5ce76e86db 100644\n--- a/accel/mshv/mshv-all.c\n+++ b/accel/mshv/mshv-all.c\n@@ -156,6 +156,7 @@ static int set_synthetic_proc_features(int vm_fd)\n features.tb_flush_hypercalls = 1;\n features.synthetic_cluster_ipi = 1;\n features.direct_synthetic_timers = 1;\n+ features.access_vp_regs = 1;\n \n mshv_arch_amend_proc_features(&features);\n \ndiff --git a/include/hw/hyperv/hvhdk.h b/include/hw/hyperv/hvhdk.h\nindex 2e1ef80972..3807ed4302 100644\n--- a/include/hw/hyperv/hvhdk.h\n+++ b/include/hw/hyperv/hvhdk.h\n@@ -94,11 +94,16 @@ union hv_partition_synthetic_processor_features {\n */\n uint64_t access_partition_reference_tsc:1;\n \n+#if defined(__x86_64__)\n+\n /*\n * Partition has access to the guest idle reg. Corresponds to\n * access_guest_idle_reg privilege.\n */\n uint64_t access_guest_idle_reg:1;\n+#else\n+ uint64_t reserved_z10:1;\n+#endif\n \n /*\n * Partition has access to frequency regs. corresponds to\n@@ -110,11 +115,16 @@ union hv_partition_synthetic_processor_features {\n uint64_t reserved_z13:1; /* Reserved for access_root_scheduler_reg */\n uint64_t reserved_z14:1; /* Reserved for access_tsc_invariant_controls */\n \n+#if defined(__x86_64__)\n+\n /*\n * Extended GVA ranges for HvCallFlushVirtualAddressList hypercall.\n * Corresponds to privilege.\n */\n uint64_t enable_extended_gva_ranges_for_flush_virtual_address_list:1;\n+#else\n+ uint64_t reserved_z15:1;\n+#endif\n \n uint64_t reserved_z16:1; /* Reserved for access_vsm. */\n uint64_t reserved_z17:1; /* Reserved for access_vp_registers. */\n@@ -161,13 +171,92 @@ union hv_partition_synthetic_processor_features {\n /* HvCallRetargetDeviceInterrupt is supported. */\n uint64_t retarget_device_interrupt:1;\n \n+#if defined(__x86_64__)\n /* HvCallRestorePartitionTime is supported. */\n uint64_t restore_time:1;\n \n /* EnlightenedVmcs nested enlightenment is supported. */\n uint64_t enlightened_vmcs:1;\n \n- uint64_t reserved:30;\n+ uint64_t nested_debug_ctl:1;\n+ uint64_t synthetic_time_unhalted_timer:1;\n+ uint64_t idle_spec_ctrl:1;\n+\n+#else\n+ uint64_t reserved_z31:1;\n+ uint64_t reserved_z32:1;\n+ uint64_t reserved_z33:1;\n+ uint64_t reserved_z34:1;\n+ uint64_t reserved_z35:1;\n+#endif\n+\n+#if defined(__aarch64__)\n+ /*\n+ * Register intercepts supported in V1. As more registers are supported\n+ * in future releases, new bits will be added here to prevent migration\n+ * between incompatible hosts.\n+ *\n+ * List of registers supported in V1:\n+ * 1. TPIDRRO_EL0\n+ * 2. TPIDR_EL1\n+ * 3. SCTLR_EL1 - Supports write intercept mask.\n+ * 4. VBAR_EL1\n+ * 5. TCR_EL1 - Supports write intercept mask.\n+ * 6. MAIR_EL1 - Supports write intercept mask.\n+ * 7. CPACR_EL1 - Supports write intercept mask.\n+ * 8. CONTEXTIDR_EL1\n+ * 9. PAuth keys (total 10 registers)\n+ * 10. HvArm64RegisterSyntheticException\n+ */\n+ uint64_t register_intercepts_v1:1;\n+#else\n+ uint64_t reserved_z36:1;\n+#endif\n+\n+ /* HvCallWakeVps is supported */\n+ uint64_t wake_vps:1;\n+\n+ /*\n+ * HvCallGet/SetVpRegisters is supported.\n+ * Corresponds to AccessVpRegisters privilege.\n+ * This feature only affects exo partitions.\n+ */\n+ uint64_t access_vp_regs:1;\n+\n+#if defined(__aarch64__)\n+ /* HvCallSyncContext/Ex is supported. */\n+ uint64_t sync_context:1;\n+#else\n+ uint64_t reserved_z39:1;\n+#endif /* __aarch64__ */\n+\n+ /*\n+ * Management VTL synic support is allowed.\n+ * Corresponds to the ManagementVtlSynicSupport privilege.\n+ */\n+ uint64_t management_vtl_synic_support:1;\n+\n+#if defined(__x86_64__)\n+ /*\n+ * Hypervisor supports guest mechanism to signal pending interrupts to\n+ * paravisor.\n+ */\n+ uint64_t proxy_interrupt_doorbell_support:1;\n+#else\n+ uint64_t reserved_z41:1;\n+#endif\n+\n+#if defined(__aarch64__)\n+ /* InterceptSystemResetAvailable is exposed. */\n+ uint64_t intercept_system_reset:1;\n+#else\n+ uint64_t reserved_z42:1;\n+#endif\n+\n+ /* Hypercalls for host MMIO operations are available. */\n+ uint64_t mmio_hypercalls:1;\n+\n+ uint64_t reserved:20;\n };\n };\n \n","prefixes":["v2","07/14"]}