{"id":2219134,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2219134/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260402-mshv_accel_arm64_supp-v2-12-754895c15e9e@linux.microsoft.com>","date":"2026-04-02T12:52:39","name":"[v2,12/14] include/hw/hyperv: adjust hv_interrupt_control structure for arm64","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"d45134d79191cfc5bf5c933ef46307b113218e31","submitter":{"id":92925,"url":"http://patchwork.ozlabs.org/api/1.0/people/92925/?format=json","name":"Aastha Rawat","email":"aastharawat@linux.microsoft.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260402-mshv_accel_arm64_supp-v2-12-754895c15e9e@linux.microsoft.com/mbox/","series":[{"id":498484,"url":"http://patchwork.ozlabs.org/api/1.0/series/498484/?format=json","date":"2026-04-02T12:52:39","name":"Add ARM64 support for MSHV accelerator","version":2,"mbox":"http://patchwork.ozlabs.org/series/498484/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2219134/checks/","tags":{},"headers":{"Return-Path":"<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.microsoft.com header.i=@linux.microsoft.com\n header.a=rsa-sha256 header.s=default header.b=EbER5pjn;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=linux.microsoft.com","X-Spam_score_int":"-42","X-Spam_score":"-4.3","X-Spam_bar":"----","X-Spam_report":"(-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development <qemu-devel.nongnu.org>","List-Unsubscribe":"<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>","List-Archive":"<https://lists.nongnu.org/archive/html/qemu-devel>","List-Post":"<mailto:qemu-devel@nongnu.org>","List-Help":"<mailto:qemu-devel-request@nongnu.org?subject=help>","List-Subscribe":"<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: \"Anirudh Rayabharam (Microsoft)\" <anirudh@anirudhrb.com>\n\nAdd the arm64 specific fields to the hv_interrupt_control struct and\nadjust the existing usage accordingly. mshv_request_interrupt is only\nneeded only for x86 so compile it out entirely for arm64.\n\nSigned-off-by: Anirudh Rayabharam (Microsoft) <anirudh@anirudhrb.com>\n---\n accel/mshv/irq.c               |  2 ++\n include/hw/hyperv/hvgdk_mini.h | 25 +++++++++++++++++++++++++\n include/system/mshv.h          |  2 ++\n 3 files changed, 29 insertions(+)","diff":"diff --git a/accel/mshv/irq.c b/accel/mshv/irq.c\nindex 3c238c33c3..a391d7db86 100644\n--- a/accel/mshv/irq.c\n+++ b/accel/mshv/irq.c\n@@ -310,6 +310,7 @@ int mshv_irqchip_update_msi_route(int virq, MSIMessage msg, PCIDevice *dev)\n     return 0;\n }\n \n+#if defined(__x86_64__)\n int mshv_request_interrupt(MshvState *mshv_state, uint32_t interrupt_type, uint32_t vector,\n                            uint32_t vp_index, bool logical_dest_mode,\n                            bool level_triggered)\n@@ -346,6 +347,7 @@ int mshv_request_interrupt(MshvState *mshv_state, uint32_t interrupt_type, uint3\n     }\n     return 0;\n }\n+#endif\n \n void mshv_irqchip_commit_routes(void)\n {\ndiff --git a/include/hw/hyperv/hvgdk_mini.h b/include/hw/hyperv/hvgdk_mini.h\nindex 84b3c6af5f..eb766734d6 100644\n--- a/include/hw/hyperv/hvgdk_mini.h\n+++ b/include/hw/hyperv/hvgdk_mini.h\n@@ -506,13 +506,38 @@ typedef struct hv_input_set_vp_registers {\n     struct hv_register_assoc elements[];\n } hv_input_set_vp_registers;\n \n+enum hv_interrupt_type {\n+#if defined(__x86_64__)\n+    HV_X64_INTERRUPT_TYPE_FIXED             = 0x0000,\n+    HV_X64_INTERRUPT_TYPE_LOWESTPRIORITY    = 0x0001,\n+    HV_X64_INTERRUPT_TYPE_SMI               = 0x0002,\n+    HV_X64_INTERRUPT_TYPE_REMOTEREAD        = 0x0003,\n+    HV_X64_INTERRUPT_TYPE_NMI               = 0x0004,\n+    HV_X64_INTERRUPT_TYPE_INIT              = 0x0005,\n+    HV_X64_INTERRUPT_TYPE_SIPI              = 0x0006,\n+    HV_X64_INTERRUPT_TYPE_EXTINT            = 0x0007,\n+    HV_X64_INTERRUPT_TYPE_LOCALINT0         = 0x0008,\n+    HV_X64_INTERRUPT_TYPE_LOCALINT1         = 0x0009,\n+    HV_X64_INTERRUPT_TYPE_MAXIMUM           = 0x000A,\n+#elif defined(__aarch64__)\n+    HV_ARM64_INTERRUPT_TYPE_FIXED           = 0x0000,\n+    HV_ARM64_INTERRUPT_TYPE_MAXIMUM         = 0x0008,\n+#endif\n+};\n+\n union hv_interrupt_control {\n     uint64_t as_uint64;\n     struct {\n         uint32_t interrupt_type; /* enum hv_interrupt type */\n+#if defined(__x86_64__)\n         uint32_t level_triggered:1;\n         uint32_t logical_dest_mode:1;\n         uint32_t rsvd:30;\n+#elif defined(__aarch64__)\n+        uint32_t rsvd1:2;\n+        uint32_t asserted:1;\n+        uint32_t rsvd2:29;\n+#endif\n     };\n };\n \ndiff --git a/include/system/mshv.h b/include/system/mshv.h\nindex 75286baf16..0db18fcee9 100644\n--- a/include/system/mshv.h\n+++ b/include/system/mshv.h\n@@ -47,10 +47,12 @@ extern bool mshv_allowed;\n typedef struct MshvState MshvState;\n extern MshvState *mshv_state;\n \n+#if defined(__x86_64__)\n /* interrupt */\n int mshv_request_interrupt(MshvState *mshv_state, uint32_t interrupt_type, uint32_t vector,\n                            uint32_t vp_index, bool logical_destination_mode,\n                            bool level_triggered);\n+#endif\n \n int mshv_irqchip_add_msi_route(int vector, PCIDevice *dev);\n int mshv_irqchip_update_msi_route(int virq, MSIMessage msg, PCIDevice *dev);\n","prefixes":["v2","12/14"]}