{"id":2218693,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2218693/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260401170454.32045-3-yodel.eldar@yodel.dev>","date":"2026-04-01T17:04:52","name":"[RFC,2/4] alpha: Propagate CPU index via MemTxAttrs","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"e3d7d3153dfa7c2e92f2984b69500f13baf0191c","submitter":{"id":92094,"url":"http://patchwork.ozlabs.org/api/1.0/people/92094/?format=json","name":"Yodel Eldar","email":"yodel.eldar@yodel.dev"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401170454.32045-3-yodel.eldar@yodel.dev/mbox/","series":[{"id":498370,"url":"http://patchwork.ozlabs.org/api/1.0/series/498370/?format=json","date":"2026-04-01T17:04:50","name":"alpha: Decouple the CPU and Typhoon","version":1,"mbox":"http://patchwork.ozlabs.org/series/498370/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2218693/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=yodel.dev header.i=@yodel.dev header.a=rsa-sha256\n header.s=rsa2048 header.b=DhaU0sya;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fmBFj5fhBz1yGw\n\tfor ; Thu, 02 Apr 2026 04:05:45 +1100 (AEDT)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1w7z0O-0000vL-Pu; Wed, 01 Apr 2026 13:05:28 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1)\n (envelope-from )\n id 1w7z09-0000pk-O0\n for qemu-devel@nongnu.org; Wed, 01 Apr 2026 13:05:11 -0400","from v512.v5f06b487.use4.send.mailgun.net ([143.55.232.12])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1)\n (envelope-from )\n id 1w7z07-0007ss-A9\n for qemu-devel@nongnu.org; Wed, 01 Apr 2026 13:05:08 -0400","from mail.yodel.dev (mail.yodel.dev [35.209.39.246]) by\n ff02f649880f4c1d5d70100ea9aa6e7e10e475320cb5153f37db282a819a7e15 with SMTP id\n 69cd503a909492175f9ecf6f; Wed, 01 Apr 2026 17:04:58 GMT"],"X-Mailgun-Sid":"WyI4ZDFlNiIsInFlbXUtZGV2ZWxAbm9uZ251Lm9yZyIsIjk3NjA3ZSJd","X-Mailgun-Sending-Ip":"143.55.232.12","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=yodel.dev;\n s=rsa2048; t=1775063098;\n bh=sbl1/SbOW5RNXGHHar18gl/ANw6AoNz11ZBRCd42A2E=;\n h=X-Mailgun-Dkim:From:To:Cc:Subject:Date:Message-ID:In-Reply-To:\n References:MIME-Version:Content-Transfer-Encoding:From:Reply-to:\n Subject:Date:Message-id:To:Cc:Mime-version:Content-type:\n Content-transfer-encoding:In-reply-to:References;\n b=DhaU0sya4y8ECW/vFKKDG5ogOzFK5AalKAx6xq+fISybhtbjKZKPdQKU9ZrgEoWoM\n X1ryqziLXsm0RFuOC4uvZ+p5hxE+SKt5yvp6QndFcc3LvrcUrqoAgSTCVkt2k+cw+S\n zq1POc88TbK9ejvPTMf/qH0ktHRzF1pXjO4blrJUJVVBORkYxU5DSHSDaHWdni608w\n 4SfTz6Jh9LxdMLOFZVlJLFbiaMNr/zVTKiqXYhf++DTX2z1k7mFH97e39SNQ4i8U70\n 8+Kz4gBbpvKP+93GQqZ4CBPGzlQL9nFkbXU4IAs8eWt23f1b0nJhFYZInBsEBNXsoq\n M+PfgLgo1Hq8w==","X-Mailgun-Dkim":["no","no"],"From":"\"Yodel Eldar\" ","To":"qemu-devel@nongnu.org","Cc":"Richard Henderson , =?utf-8?q?Philippe_Mat?=\n\t=?utf-8?q?hieu-Daud=C3=A9?= ,\n Yodel Eldar ","Subject":"[RFC PATCH 2/4] alpha: Propagate CPU index via MemTxAttrs","Date":"Wed, 1 Apr 2026 12:04:52 -0500","Message-ID":"<20260401170454.32045-3-yodel.eldar@yodel.dev>","In-Reply-To":"<20260401170454.32045-1-yodel.eldar@yodel.dev>","References":"<20260401170454.32045-1-yodel.eldar@yodel.dev>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=143.55.232.12;\n envelope-from=bounce+0e9322.97607e-qemu-devel=nongnu.org@yodel.dev;\n helo=v512.v5f06b487.use4.send.mailgun.net","X-Spam_score_int":"0","X-Spam_score":"-0.1","X-Spam_bar":"/","X-Spam_report":"(-0.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n HELO_STATIC_HOST=-0.001, RCVD_IN_MSPIKE_H2=-0.01,\n RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1, RCVD_IN_VALIDITY_RPBL_BLOCKED=1,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Yodel Eldar \n\nCurrently, a read of the Typhoon Cchip's MISC register\ndereferences current_cpu for the CPU index. To decouple\nTyphoon from the CPU, let's instead pass the CPU index\nthrough the requester_id attribute of the memory transaction.\n\nSigned-off-by: Yodel Eldar \n---\n hw/alpha/typhoon.c | 7 ++++---\n target/alpha/helper.c | 15 ++++++++++++---\n 2 files changed, 16 insertions(+), 6 deletions(-)","diff":"diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c\nindex 26580664d8..5dadfa7691 100644\n--- a/hw/alpha/typhoon.c\n+++ b/hw/alpha/typhoon.c\n@@ -74,7 +74,6 @@ static MemTxResult cchip_read(void *opaque, hwaddr addr,\n uint64_t *data, unsigned size,\n MemTxAttrs attrs)\n {\n- CPUState *cpu = current_cpu;\n TyphoonState *s = opaque;\n uint64_t ret = 0;\n \n@@ -90,10 +89,12 @@ static MemTxResult cchip_read(void *opaque, hwaddr addr,\n /* All sorts of stuff related to real DRAM. */\n break;\n \n- case 0x0080:\n+ case 0x0080: {\n /* MISC: Miscellaneous Register. */\n- ret = s->cchip.misc | (cpu->cpu_index & 3);\n+ uint64_t cpu_index = attrs.requester_id & 3;\n+ ret = s->cchip.misc | cpu_index;\n break;\n+ }\n \n case 0x00c0:\n /* MPD: Memory Presence Detect Register. */\ndiff --git a/target/alpha/helper.c b/target/alpha/helper.c\nindex 179dc2dc7a..bebb0e4804 100644\n--- a/target/alpha/helper.c\n+++ b/target/alpha/helper.c\n@@ -164,13 +164,19 @@ void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address,\n env->trap_arg2 = cause;\n }\n #else\n+static inline QEMU_ALWAYS_INLINE\n+MemTxAttrs alpha_cpu_get_mem_attrs(const CPUState *cs)\n+{\n+ return (MemTxAttrs){ .requester_id = cs->cpu_index };\n+}\n+\n /* Returns the OSF/1 entMM failure indication, or -1 on success. */\n static int get_physical_address(CPUAlphaState *env, vaddr addr,\n int prot_need, int mmu_idx,\n hwaddr *pphys, int *pprot)\n {\n- const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;\n CPUState *cs = env_cpu(env);\n+ const MemTxAttrs attrs = alpha_cpu_get_mem_attrs(cs);\n target_long saddr = addr;\n hwaddr phys = 0;\n uint64_t L1pte, L2pte, L3pte;\n@@ -327,8 +333,11 @@ bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,\n cpu_loop_exit_restore(cs, retaddr);\n }\n \n- tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK,\n- prot, mmu_idx, TARGET_PAGE_SIZE);\n+ tlb_set_page_with_attrs(cs, addr & TARGET_PAGE_MASK,\n+ phys & TARGET_PAGE_MASK,\n+ alpha_cpu_get_mem_attrs(cs),\n+ prot, mmu_idx, TARGET_PAGE_SIZE);\n+\n return true;\n }\n \n","prefixes":["RFC","2/4"]}