{"id":2198402,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2198402/?format=json","project":{"id":22,"url":"http://patchwork.ozlabs.org/api/1.0/projects/22/?format=json","name":"HostAP Development","link_name":"hostap","list_id":"hostap.lists.infradead.org","list_email":"hostap@lists.infradead.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260219202514.5781-4-andrei.otcheretianski@intel.com>","date":"2026-02-19T20:24:19","name":"[03/58] NAN: Add Data path and scheduling definition","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"d75b66c06a4e641850d6769dfa3fe2a67307569f","submitter":{"id":62065,"url":"http://patchwork.ozlabs.org/api/1.0/people/62065/?format=json","name":"Andrei Otcheretianski","email":"andrei.otcheretianski@intel.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/hostap/patch/20260219202514.5781-4-andrei.otcheretianski@intel.com/mbox/","series":[{"id":492721,"url":"http://patchwork.ozlabs.org/api/1.0/series/492721/?format=json","date":"2026-02-19T20:24:21","name":"NAN: Add NAN Data Path (NDP) support","version":1,"mbox":"http://patchwork.ozlabs.org/series/492721/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2198402/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=lists.infradead.org header.i=@lists.infradead.org\n header.a=rsa-sha256 header.s=bombadil.20210309 header.b=DJTJ7/Q7;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=mrg0h8H5;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=none (no SPF record) smtp.mailfrom=lists.infradead.org\n (client-ip=2607:7c80:54:3::133; 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a=\"90039909\"","E=Sophos;i=\"6.21,300,1763452800\";\n d=\"scan'208\";a=\"90039909\"","E=Sophos;i=\"6.21,300,1763452800\";\n d=\"scan'208\";a=\"219153696\""],"X-ExtLoop1":"1","From":"Andrei Otcheretianski ","To":"hostap@lists.infradead.org,\n\tvamsin@qti.qualcomm.com,\n\tvganneva@qti.qualcomm.com,\n\tmaheshkkv@google.com","Cc":"Ilan Peer ","Subject":"[PATCH 03/58] NAN: Add Data path and scheduling definition","Date":"Thu, 19 Feb 2026 22:24:19 +0200","Message-ID":"<20260219202514.5781-4-andrei.otcheretianski@intel.com>","X-Mailer":"git-send-email 2.52.0","In-Reply-To":"<20260219202514.5781-1-andrei.otcheretianski@intel.com>","References":"<20260219202514.5781-1-andrei.otcheretianski@intel.com>","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20260219_122541_192263_E39880FE ","X-CRM114-Status":"GOOD ( 15.43 )","X-Spam-Score":"-4.4 (----)","X-Spam-Report":"Spam detection software,\n running on the system \"bombadil.infradead.org\",\n has NOT identified this incoming email as spam. The original\n message has been attached to this so you can view it or label\n similar future email. If you have any questions, see\n the administrator of that system for details.\n Content preview: From: Ilan Peer Add definitions for\n NAN Data Path and NAN scheduling attributes etc. While at it, align some of\n the existing definitions.\n Content analysis details: (-4.4 points, 5.0 required)\n pts rule name description\n ---- ----------------------\n --------------------------------------------------\n -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/,\n medium trust\n [198.175.65.10 listed in list.dnswl.org]\n 0.0 RCVD_IN_VALIDITY_SAFE_BLOCKED RBL: ADMINISTRATOR NOTICE: The query to\n Validity was blocked. See\n https://knowledge.validity.com/hc/en-us/articles/20961730681243\n for more information.\n [198.175.65.10 listed in sa-accredit.habeas.com]\n 0.0 RCVD_IN_VALIDITY_CERTIFIED_BLOCKED RBL: ADMINISTRATOR NOTICE: The\n query to Validity was blocked. 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"Hostap\" ","Errors-To":"hostap-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"},"content":"From: Ilan Peer \n\nAdd definitions for NAN Data Path and NAN scheduling\nattributes etc.\n\nWhile at it, align some of the existing definitions.\n\nSigned-off-by: Ilan Peer \n---\n src/common/nan_defs.h | 381 ++++++++++++++++++++++++++++++++++++++++--\n 1 file changed, 366 insertions(+), 15 deletions(-)","diff":"diff --git a/src/common/nan_defs.h b/src/common/nan_defs.h\nindex 611e004238..fbec4c8455 100644\n--- a/src/common/nan_defs.h\n+++ b/src/common/nan_defs.h\n@@ -1,6 +1,7 @@\n /*\n * NAN (Wi-Fi Aware) definitions\n * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ * Copyright (c) 2026, Intel Corporation\n *\n * This software may be distributed under the terms of the BSD license.\n * See README for more details.\n@@ -9,6 +10,27 @@\n #ifndef NAN_DEFS_H\n #define NAN_DEFS_H\n \n+#define NAN_TYPE_SDF 0x13\n+#define NAN_TYPE_NAF 0x18\n+\n+/* See Section 9.4.1 */\n+enum nan_subtype {\n+\tNAN_SUBTYPE_INVALID\t\t = 0,\n+\tNAN_SUBTYPE_RANGING_REQUEST\t\t= 1,\n+\tNAN_SUBTYPE_RANGING_RESPONSE\t\t= 2,\n+\tNAN_SUBTYPE_RANGING_TERMINATION\t\t= 3,\n+\tNAN_SUBTYPE_RANGING_REPORT\t\t= 4,\n+\tNAN_SUBTYPE_DATA_PATH_REQUEST\t\t= 5,\n+\tNAN_SUBTYPE_DATA_PATH_RESPONSE\t\t= 6,\n+\tNAN_SUBTYPE_DATA_PATH_CONFIRM\t\t= 7,\n+\tNAN_SUBTYPE_DATA_PATH_KEY_INSTALL\t= 8,\n+\tNAN_SUBTYPE_DATA_PATH_TERMINATION\t= 9,\n+\tNAN_SUBTYPE_SCHEDULE_REQUEST\t\t= 10,\n+\tNAN_SUBTYPE_SCHEDULE_RESPONSE\t\t= 11,\n+\tNAN_SUBTYPE_SCHEDULE_CONFIRM\t\t= 12,\n+\tNAN_SUBTYPE_SCHEDULE_UPDATE_NOTIF\t= 13,\n+};\n+\n enum nan_attr_id {\n \tNAN_ATTR_MASTER_INDICATION = 0x00,\n \tNAN_ATTR_CLUSTER = 0x01,\n@@ -54,15 +76,33 @@ enum nan_attr_id {\n \tNAN_ATTR_VENDOR_SPECIFIC = 0xDD,\n };\n \n+/* See Table 43 */\n+enum nan_reason {\n+\tNAN_REASON_RESERVED = 0,\n+\tNAN_REASON_UNSPECIFIED_REASON = 1,\n+\tNAN_REASON_RESOURCE_LIMITATION = 2,\n+\tNAN_REASON_INVALID_PARAMETERS = 3,\n+\tNAN_REASON_FTM_PARAMETERS_INCAPABLE = 4,\n+\tNAN_REASON_NO_MOVEMENT = 5,\n+\tNAN_REASON_INVALID_AVAILABILITY = 6,\n+\tNAN_REASON_IMMUTABLE_UNACCEPTABLE = 7,\n+\tNAN_REASON_SECURITY_POLICY = 8,\n+\tNAN_REASON_QOS_UNACCEPTABLE = 9,\n+\tNAN_REASON_NDP_REJECTED = 10,\n+\tNAN_REASON_NDL_UNACCEPTABLE = 11,\n+\tNAN_REASON_RANGING_SCHED_NOT_ACCEPT = 12,\n+\tNAN_REASON_PAIR_BOOTSTRAP_REJECTED = 13,\n+};\n+\n /* Service Descriptor attribute (SDA) */\n \n /* Service Control field */\n-#define NAN_SRV_CTRL_TYPE_MASK (BIT(0) | BIT(1))\n-#define NAN_SRV_CTRL_MATCHING_FILTER BIT(2)\n-#define NAN_SRV_CTRL_RESP_FILTER BIT(3)\n-#define NAN_SRV_CTRL_SRV_INFO BIT(4)\n-#define NAN_SRV_CTRL_DISCOVERY_RANGE_LIMITED BIT(5)\n-#define NAN_SRV_CTRL_BINDING_BITMAP BIT(6)\n+#define NAN_SRV_CTRL_TYPE_MASK (BIT(0) | BIT(1))\n+#define NAN_SRV_CTRL_MATCHING_FILTER BIT(2)\n+#define NAN_SRV_CTRL_RESP_FILTER BIT(3)\n+#define NAN_SRV_CTRL_SRV_INFO BIT(4)\n+#define NAN_SRV_CTRL_DISCOVERY_RANGE_LIMITED BIT(5)\n+#define NAN_SRV_CTRL_BINDING_BITMAP BIT(6)\n \n enum nan_service_control_type {\n \tNAN_SRV_CTRL_PUBLISH = 0,\n@@ -73,16 +113,16 @@ enum nan_service_control_type {\n /* Service Descriptor Extension attribute (SDEA) */\n \n /* SDEA Control field */\n-#define NAN_SDEA_CTRL_FSD_REQ BIT(0)\n-#define NAN_SDEA_CTRL_FSD_GAS BIT(1)\n-#define NAN_SDEA_CTRL_DATA_PATH_REQ BIT(2)\n+#define NAN_SDEA_CTRL_FSD_REQ BIT(0)\n+#define NAN_SDEA_CTRL_FSD_GAS BIT(1)\n+#define NAN_SDEA_CTRL_DATA_PATH_REQ BIT(2)\n #define NAN_SDEA_CTRL_DATA_PATH_TYPE BIT(3)\n-#define NAN_SDEA_CTRL_QOS_REQ BIT(5)\n-#define NAN_SDEA_CTRL_SECURITY_REQ BIT(6)\n-#define NAN_SDEA_CTRL_RANGING_REQ BIT(7)\n-#define NAN_SDEA_CTRL_RANGE_LIMIT BIT(8)\n-#define NAN_SDEA_CTRL_SRV_UPD_INDIC BIT(9)\n-#define NAN_SDEA_CTRL_GTK_REQ BIT(10)\n+#define NAN_SDEA_CTRL_QOS_REQ BIT(5)\n+#define NAN_SDEA_CTRL_SECURITY_REQ BIT(6)\n+#define NAN_SDEA_CTRL_RANGING_REQ BIT(7)\n+#define NAN_SDEA_CTRL_RANGE_LIMIT BIT(8)\n+#define NAN_SDEA_CTRL_SRV_UPD_INDIC BIT(9)\n+#define NAN_SDEA_CTRL_GTK_REQ BIT(10)\n \n enum nan_service_protocol_type {\n \tNAN_SRV_PROTO_BONJOUR = 1,\n@@ -105,4 +145,315 @@ enum nan_service_protocol_type {\n \n #define NAN_USD_DEFAULT_FREQ 2437\n \n+/* MAP ID: See Table 79 (Device Capability) */\n+#define NAN_DEV_CAPA_MAP_ID_DONT_APPLY_ALL BIT(0)\n+#define NAN_DEV_CAPA_MAP_ID_POS 1\n+#define NAN_DEV_CAPA_MAP_ID_MASK (BIT(1) | BIT(2) | BIT(3) \\\n+\t\t\t\t\t BIT(4))\n+\n+/* Supported bands: See Table 79 (Device Capability) */\n+#define NAN_DEV_CAPA_SBAND_SUB_1G BIT(1)\n+#define NAN_DEV_CAPA_SBAND_2G BIT(2)\n+#define NAN_DEV_CAPA_SBAND_5G BIT(4)\n+#define NAN_DEV_CAPA_SBAND_6G BIT(7)\n+\n+/* See Table 80 (Committed Discovery Window Information Field) */\n+#define NAN_CDW_INFO_2G_POS 0\n+#define NAN_CDW_INFO_2G_MASK (BIT(0) | BIT(1) | BIT(2))\n+#define NAN_CDW_INFO_5G_POS 3\n+#define NAN_CDW_INFO_5G_MASK (BIT(3) | BIT(4) | BIT(5))\n+#define NAN_CDW_INFO_2G_OVERRIDE_POS 6\n+#define NAN_CDW_INFO_2G_OVERRIDE_MASK (BIT(6) | BIT(7) | BIT(8) | BIT(9))\n+#define NAN_CDW_INFO_5G_OVERRIDE_POS 10\n+#define NAN_CDW_INFO_5G_OVERRIDE_MASK (BIT(10) | BIT(11) | BIT(12) | BIT(13))\n+\n+/* See Table 81 (Operation Mode Field) */\n+#define NAN_DEV_CAPA_OP_MODE_PHY_MODE (BIT(0) | BIT(4))\n+#define NAN_DEV_CAPA_OP_MODE_PHY_MODE_VHT BIT(0)\n+#define NAN_DEV_CAPA_OP_MODE_PHY_MODE_HE BIT(4)\n+#define NAN_DEV_CAPA_OP_MODE_HE_VHT_80P80 BIT(1)\n+#define NAN_DEV_CAPA_OP_MODE_HE_VHT_160 BIT(2)\n+\n+/* Antennas: See Table 79 (Device Capability) */\n+#define NAN_DEV_CAPA_TX_ANT_POS 0\n+#define NAN_DEV_CAPA_TX_ANT_MASK 0x0f\n+#define NAN_DEV_CAPA_RX_ANT_POS 4\n+#define NAN_DEV_CAPA_RX_ANT_MASK 0xf0\n+\n+/* Capabilities: See Table 79 (Device Capability) */\n+#define NAN_DEV_CAPA_DFS_MASTER BIT(0)\n+#define NAN_DEV_CAPA_EXT_KEY_ID BIT(1)\n+#define NAN_DEV_CAPA_SIM_NDP_RX BIT(2)\n+#define NAN_DEV_CAPA_NDPE_ATTR_SUPP BIT(3)\n+#define NAN_DEV_CAPA_S3 BIT(4)\n+\n+/* Device Capability Attribute: See Table 79 (Device Capability) */\n+struct nan_device_capa {\n+\tu8 map_id;\n+\tle16 cdw_info;\n+\tu8 supported_bands;\n+\tu8 op_mode;\n+\tu8 ant;\n+\tle16 channel_switch_time;\n+\tu8 capa;\n+} STRUCT_PACKED;\n+\n+#define NAN_NDP_TYPE_POS 0\n+#define NAN_NDP_TYPE_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3))\n+#define NAN_NDP_STATUS_POS 4\n+#define NAN_NDP_STATUS_MASK (BIT(4) | BIT(5) | BIT(6) | BIT(7))\n+\n+/* NDP type: See Table 82 (NDP attribute format) */\n+enum nan_ndp_type {\n+\tNAN_NDP_TYPE_REQUEST\t\t= 0,\n+\tNAN_NDP_TYPE_RESPONSE\t\t= 1,\n+\tNAN_NDP_TYPE_CONFIRM\t\t= 2,\n+\tNAN_NDP_TYPE_SECURITY_INSTALL\t= 3,\n+\tNAN_NDP_TYPE_TERMINATE\t\t= 4,\n+};\n+\n+/* NDP status: See Table 82 (NDP attribute format) */\n+enum nan_ndp_status {\n+\tNAN_NDP_STATUS_CONTINUED = 0,\n+\tNAN_NDP_STATUS_ACCEPTED = 1,\n+\tNAN_NDP_STATUS_REJECTED = 2,\n+};\n+\n+/* See Table 84 (NDP Control field) */\n+#define NAN_NDP_CTRL_CONFIRM_REQUIRED BIT(0)\n+/* Bit position 1 is reserved in the spec */\n+#define NAN_NDP_CTRL_SECURITY_PRESENT BIT(2)\n+#define NAN_NDP_CTRL_PUBLISH_ID_PRESENT BIT(3)\n+#define NAN_NDP_CTRL_RESPONDER_NDI_PRESENT BIT(4)\n+#define NAN_NDP_CTRL_SPEC_INFO_PRESENT BIT(5)\n+\n+/* NDP type: See Table 82 (NDP attribute format)\n+ * Note: the structure does not include the id and length.\n+ */\n+struct ieee80211_ndp {\n+\tu8 dialog_token;\n+\tu8 type_and_status;\n+\tu8 reason_code;\n+\tu8 initiator_ndi[ETH_ALEN];\n+\tu8 ndp_id;\n+\tu8 ndp_ctrl;\n+\n+\t/* followed by optional fields based on ndp_ctrl */\n+\tu8 optional[0];\n+} STRUCT_PACKED;\n+\n+/* See Table 97 (Time Bitmap Control field format) */\n+#define NAN_TIME_BM_CTRL_BIT_DURATION_POS 0\n+#define NAN_TIME_BM_CTRL_BIT_DURATION_MASK (BIT(0) | BIT(1) | BIT(2))\n+#define NAN_TIME_BM_CTRL_BIT_DURATION_16_TU 0\n+#define NAN_TIME_BM_CTRL_BIT_DURATION_32_TU 1\n+#define NAN_TIME_BM_CTRL_BIT_DURATION_64_TU 2\n+#define NAN_TIME_BM_CTRL_BIT_DURATION_128_TU 3\n+\n+#define NAN_TIME_BM_CTRL_PERIOD_POS 3\n+#define NAN_TIME_BM_CTRL_PERIOD_MASK (BIT(3) | BIT(4) | BIT(5))\n+#define NAN_TIME_BM_CTRL_PERIOD_NONE 0\n+\n+#define NAN_TIME_BM_CTRL_START_OFFSET_POS 6\n+#define NAN_TIME_BM_CTRL_START_OFFSET_MASK (BIT(6) | BIT(7) | BIT(8) | \\\n+\t\t\t\t\t BIT(9) | BIT(10) | BIT(11) | \\\n+\t\t\t\t\t BIT(12) | BIT(13) | BIT(14))\n+\n+/* See Table 96 (Entry Control Filed for NAN Availability attribute) */\n+#define NAN_AVAIL_ENTRY_CTRL_TYPE_COMMITTED BIT(0)\n+#define NAN_AVAIL_ENTRY_CTRL_TYPE_POTENTIAL BIT(1)\n+#define NAN_AVAIL_ENTRY_CTRL_TYPE_COND BIT(2)\n+#define NAN_AVAIL_ENTRY_CTRL_TYPE_MASK \\\n+\t(NAN_AVAIL_ENTRY_CTRL_TYPE_COMMITTED | \\\n+\t NAN_AVAIL_ENTRY_CTRL_TYPE_POTENTIAL | \\\n+\t NAN_AVAIL_ENTRY_CTRL_TYPE_COND)\n+\n+#define NAN_AVAIL_ENTRY_CTRL_USAGE_PREF_POS 3\n+#define NAN_AVAIL_ENTRY_CTRL_USAGE_PREF_MASK (BIT(3) | BIT(4))\n+#define NAN_AVAIL_ENTRY_CTRL_UTIL_UNKNOWN 7\n+#define NAN_AVAIL_ENTRY_CTRL_UTIL_MAX 5\n+#define NAN_AVAIL_ENTRY_CTRL_UTIL_POS 5\n+#define NAN_AVAIL_ENTRY_CTRL_UTIL_MASK (BIT(5) | BIT(6) | BIT(7))\n+#define NAN_AVAIL_ENTRY_CTRL_RX_NSS_POS 8\n+#define NAN_AVAIL_ENTRY_CTRL_RX_NSS_MASK (BIT(8) | BIT(9) | BIT(10) | \\\n+\t\t\t\t\t BIT(11))\n+#define NAN_AVAIL_ENTRY_CTRL_TBM_PRESENT BIT(12)\n+\n+/* See Table 99 (List of Band Entries) */\n+enum nan_band_entry {\n+\tNAN_BAND_ENTRY_SUB_1G = 1,\n+\tNAN_BAND_ENTRY_2G = 2,\n+\tNAN_BAND_ENTRY_5G = 4,\n+\tNAN_BAND_ENTRY_6G = 7,\n+};\n+\n+/* See Table 100 (Channel Entry format for the NAN Availability attribute) */\n+struct nan_chan_entry {\n+\tu8 op_class;\n+\tle16 chan_bitmap;\n+\tu8 pri_chan_bitmap;\n+\n+\t/* This field is optional. It is present only if\n+\t * NAN_BAND_CHAN_CTRL_NON_CONT_BW is set\n+\t */\n+\tle16 aux_chan_bitmap;\n+} STRUCT_PACKED;\n+\n+/*\n+ * Channel entry only contains the aux_chan_btm field for 80+80MHz operating\n+ * class. See Table 100.\n+ */\n+#define NAN_CHAN_ENRTY_MIN_LEN 4\n+#define NAN_CHAN_ENRTY_80P80_LEN 6\n+\n+/*\n+ * See Table 98 (Band/Channel Entries List field format for the NAN Availability\n+ * attribute)\n+ */\n+#define NAN_BAND_CHAN_CTRL_TYPE BIT(0)\n+#define NAN_BAND_CHAN_CTRL_NON_CONT_BW BIT(1)\n+/* Bit positions 2 and 3 are reserved in the spec */\n+#define NAN_BAND_CHAN_CTRL_NUM_ENTRIES_POS 4\n+#define NAN_BAND_CHAN_CTRL_NUM_ENTRIES_MASK (BIT(4) | BIT(5) | BIT(6) | BIT(7))\n+\n+/*\n+ * See Table 98 (Band/Channel Entries List field format for the NAN Availability\n+ * attribute).\n+ */\n+struct nan_band_chan_list {\n+\tu8 ctrl;\n+\tu8 entries[0];\n+} STRUCT_PACKED;\n+\n+/*\n+ * See Table 95 (Availability Entry field format for the NAN Availability\n+ * attribute).\n+ */\n+struct nan_avail_ent {\n+\tle16 len;\n+\tle16 ctrl;\n+\n+\t/* followed by optional fields based on ctrl. Note that this also\n+\t * includes the inclusion of time bitmap control and length\n+\t */\n+\tu8 optional[0];\n+} STRUCT_PACKED;\n+\n+#define MIN_AVAIL_ENTRY_LEN 2\n+\n+/*\n+ * See Table 95 (Availability Entry field format for the NAN Availability\n+ * attribute). This structure represents a time bitmap related fields in the NAN\n+ * Availability entry.\n+ */\n+struct nan_tbm {\n+\tle16 ctrl;\n+\tu8 len;\n+\tu8 bitmap[0];\n+} STRUCT_PACKED;\n+\n+/* See Table 94 (Attribute Control field format for the NAN Availability\n+ * attribute)\n+ */\n+#define NAN_AVAIL_CTRL_MAP_ID_POS 0\n+#define NAN_AVAIL_CTRL_MAP_ID_MASK 0xf\n+#define NAN_AVAIL_CTRL_COMMITTED_CHANGED BIT(4)\n+#define NAN_AVAIL_CTRL_POTENTIAL_CHANGED BIT(5)\n+#define NAN_AVAIL_CTRL_PUB_AVAIL_ATTR_CHANGED BIT(6)\n+#define NAN_AVAIL_CTRL_NDC_ATTR_CHANGED BIT(7)\n+\n+/* See Table 93 (NAN Availability attribute format). ID and length not\n+ * included\n+ */\n+struct nan_avail {\n+\tu8 seq_id;\n+\tle16 ctrl;\n+\n+\t/* followed by availability entry list */\n+\tu8 optional[0];\n+} STRUCT_PACKED;\n+\n+#define NAN_SCHED_ENTRY_MAP_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3))\n+\n+/* See Table 104 (Schedule Entry format for the NDC attribute) */\n+struct nan_sched_entry {\n+\tu8 map_id;\n+\tle16 control;\n+\tu8 len;\n+\tu8 bm[0];\n+} STRUCT_PACKED;\n+\n+/* See Table 103 (Attribute Control field format for the NDC attribute) */\n+#define NAN_NDC_CTRL_SELECTED BIT(0)\n+\n+/* See Table 102 (NDC attribute format). ID and length not included */\n+struct ieee80211_ndc {\n+\tu8 ndc_id[ETH_ALEN];\n+\tu8 ctrl;\n+\tu8 sched_entries[0];\n+} STRUCT_PACKED;\n+\n+/* See Table 105 (NDL attribute format) */\n+#define NAN_NDL_TYPE_POS 0\n+#define NAN_NDL_TYPE_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3))\n+#define NAN_NDL_STATUS_POS 4\n+#define NAN_NDL_STATUS_MASK (BIT(4) | BIT(5) | BIT(6) | BIT(7))\n+\n+enum nan_ndl_type {\n+\tNAN_NDL_TYPE_REQUEST = 0,\n+\tNAN_NDL_TYPE_RESPONSE = 1,\n+\tNAN_NDL_TYPE_CONFIRM = 2,\n+};\n+\n+enum nan_ndl_status {\n+\tNAN_NDL_STATUS_CONTINUED = 0,\n+\tNAN_NDL_STATUS_ACCEPTED\t = 1,\n+\tNAN_NDL_STATUS_REJECTED\t = 2,\n+};\n+\n+/* See Table 107 (NDL Control field format) */\n+#define NAN_NDL_CTRL_PEER_ID_PRESENT BIT(0)\n+#define NAN_NDL_CTRL_IMMUT_SCHED_PRESENT BIT(1)\n+#define NAN_NDL_CTRL_NDC_ATTR_PRESENT BIT(2)\n+#define NAN_NDL_CTRL_NDL_QOS_ATTR_PRESENT BIT(3)\n+#define NAN_NDL_CTRL_MAX_IDLE_PERIOD_PRESENT BIT(4)\n+#define NAN_NDL_CTRL_NDL_TYPE BIT(5)\n+#define NAN_NDL_CTRL_NDL_SETUP_REASON_POS 6\n+#define NAN_NDL_CTRL_NDL_SETUP_REASON_MASK (BIT(6) | BIT(7))\n+\n+#define NAN_NDL_CTRL_NDL_SETUP_REASON_NDP 0x0\n+#define NAN_NDL_CTRL_NDL_SETUP_REASON_FSD_GAS 0x1\n+\n+/* See Table 105 (NDL attribute format) */\n+struct ieee80211_ndl {\n+\tu8 dialog_token;\n+\tu8 type_and_status;\n+\tu8 reason_code;\n+\tu8 ctrl;\n+\n+\t/* followed by optional fields based on ndl_ctrl */\n+\tu8 optional[0];\n+} STRUCT_PACKED;\n+\n+/* See Table 130 (Element Container attribute format) */\n+#define NAN_ELEMENT_CONTAINER_MAP_ID_VALID_POS 0\n+#define NAN_ELEMENT_CONTAINER_MAP_ID_VALID_MASK BIT(0)\n+#define NAN_ELEMENT_CONTAINER_MAP_ID_POS 1\n+#define NAN_ELEMENT_CONTAINER_MAP_ID_MASK (BIT(1) | BIT(2) | BIT(3) |\\\n+\t\t\t\t\t BIT(4))\n+\n+struct ieee80211_elemc {\n+\tu8 map_id;\n+\tu8 variable[0];\n+} STRUCT_PACKED;\n+\n+/* See Table 108 (NDL QoS attribute format) */\n+struct ieee80211_nan_qos {\n+\tu8 min_slots;\n+\tle16 max_latency;\n+} STRUCT_PACKED;\n+\n+#define NAN_QOS_MIN_SLOTS_NO_PREF 0\n+#define NAN_QOS_MAX_LATENCY_NO_PREF 0xffff\n+\n #endif /* NAN_DEFS_H */\n","prefixes":["03/58"]}