{"id":2198312,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2198312/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260219191955.83815-18-philmd@linaro.org>","date":"2026-02-19T19:19:19","name":"[v2,17/50] target/sparc: Remove MonitorDef register entries available via gdbstub","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"e9b24e3864b46e90702e3ce68802ed8c77f5b006","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/1.0/people/85046/?format=json","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260219191955.83815-18-philmd@linaro.org/mbox/","series":[{"id":492715,"url":"http://patchwork.ozlabs.org/api/1.0/series/492715/?format=json","date":"2026-02-19T19:19:03","name":"gdbstub: Build once on various targets (single-binary)","version":2,"mbox":"http://patchwork.ozlabs.org/series/492715/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2198312/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Ax/pqDxk;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::32c;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"All these registers are already provided by via gdbstub parsed XML\nand handler by the gdb_get_register() helper in the monitor/hmp.c\nfile. Remove as now unreachable code.\n\nSigned-off-by: Philippe Mathieu-Daudé \n---\n target/sparc/monitor.c | 107 -----------------------------------------\n 1 file changed, 107 deletions(-)","diff":"diff --git a/target/sparc/monitor.c b/target/sparc/monitor.c\nindex 73f15aa272d..a60671a60a4 100644\n--- a/target/sparc/monitor.c\n+++ b/target/sparc/monitor.c\n@@ -39,114 +39,8 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict)\n dump_mmu(env1);\n }\n \n-#ifndef TARGET_SPARC64\n-static target_long monitor_get_psr(Monitor *mon, const struct MonitorDef *md,\n- int val)\n-{\n- CPUArchState *env = mon_get_cpu_env(mon);\n-\n- return cpu_get_psr(env);\n-}\n-#endif\n-\n-static target_long monitor_get_reg(Monitor *mon, const struct MonitorDef *md,\n- int val)\n-{\n- CPUArchState *env = mon_get_cpu_env(mon);\n- return env->regwptr[val];\n-}\n-\n const MonitorDef monitor_defs[] = {\n- { \"g0\", offsetof(CPUSPARCState, gregs[0]) },\n- { \"g1\", offsetof(CPUSPARCState, gregs[1]) },\n- { \"g2\", offsetof(CPUSPARCState, gregs[2]) },\n- { \"g3\", offsetof(CPUSPARCState, gregs[3]) },\n- { \"g4\", offsetof(CPUSPARCState, gregs[4]) },\n- { \"g5\", offsetof(CPUSPARCState, gregs[5]) },\n- { \"g6\", offsetof(CPUSPARCState, gregs[6]) },\n- { \"g7\", offsetof(CPUSPARCState, gregs[7]) },\n- { \"o0\", 0, monitor_get_reg },\n- { \"o1\", 1, monitor_get_reg },\n- { \"o2\", 2, monitor_get_reg },\n- { \"o3\", 3, monitor_get_reg },\n- { \"o4\", 4, monitor_get_reg },\n- { \"o5\", 5, monitor_get_reg },\n- { \"o6\", 6, monitor_get_reg },\n- { \"o7\", 7, monitor_get_reg },\n- { \"l0\", 8, monitor_get_reg },\n- { \"l1\", 9, monitor_get_reg },\n- { \"l2\", 10, monitor_get_reg },\n- { \"l3\", 11, monitor_get_reg },\n- { \"l4\", 12, monitor_get_reg },\n- { \"l5\", 13, monitor_get_reg },\n- { \"l6\", 14, monitor_get_reg },\n- { \"l7\", 15, monitor_get_reg },\n- { \"i0\", 16, monitor_get_reg },\n- { \"i1\", 17, monitor_get_reg },\n- { \"i2\", 18, monitor_get_reg },\n- { \"i3\", 19, monitor_get_reg },\n- { \"i4\", 20, monitor_get_reg },\n- { \"i5\", 21, monitor_get_reg },\n- { \"i6\", 22, monitor_get_reg },\n- { \"i7\", 23, monitor_get_reg },\n- { \"pc\", offsetof(CPUSPARCState, pc) },\n- { \"npc\", offsetof(CPUSPARCState, npc) },\n- { \"y\", offsetof(CPUSPARCState, y) },\n-#ifndef TARGET_SPARC64\n- { \"psr\", 0, &monitor_get_psr, },\n- { \"wim\", offsetof(CPUSPARCState, wim) },\n-#endif\n- { \"tbr\", offsetof(CPUSPARCState, tbr) },\n- { \"fsr\", offsetof(CPUSPARCState, fsr) },\n- { \"f0\", offsetof(CPUSPARCState, fpr[0].l.upper) },\n- { \"f1\", offsetof(CPUSPARCState, fpr[0].l.lower) },\n- { \"f2\", offsetof(CPUSPARCState, fpr[1].l.upper) },\n- { \"f3\", offsetof(CPUSPARCState, fpr[1].l.lower) },\n- { \"f4\", offsetof(CPUSPARCState, fpr[2].l.upper) },\n- { \"f5\", offsetof(CPUSPARCState, fpr[2].l.lower) },\n- { \"f6\", offsetof(CPUSPARCState, fpr[3].l.upper) },\n- { \"f7\", offsetof(CPUSPARCState, fpr[3].l.lower) },\n- { \"f8\", offsetof(CPUSPARCState, fpr[4].l.upper) },\n- { \"f9\", offsetof(CPUSPARCState, fpr[4].l.lower) },\n- { \"f10\", offsetof(CPUSPARCState, fpr[5].l.upper) },\n- { \"f11\", offsetof(CPUSPARCState, fpr[5].l.lower) },\n- { \"f12\", offsetof(CPUSPARCState, fpr[6].l.upper) },\n- { \"f13\", offsetof(CPUSPARCState, fpr[6].l.lower) },\n- { \"f14\", offsetof(CPUSPARCState, fpr[7].l.upper) },\n- { \"f15\", offsetof(CPUSPARCState, fpr[7].l.lower) },\n- { \"f16\", offsetof(CPUSPARCState, fpr[8].l.upper) },\n- { \"f17\", offsetof(CPUSPARCState, fpr[8].l.lower) },\n- { \"f18\", offsetof(CPUSPARCState, fpr[9].l.upper) },\n- { \"f19\", offsetof(CPUSPARCState, fpr[9].l.lower) },\n- { \"f20\", offsetof(CPUSPARCState, fpr[10].l.upper) },\n- { \"f21\", offsetof(CPUSPARCState, fpr[10].l.lower) },\n- { \"f22\", offsetof(CPUSPARCState, fpr[11].l.upper) },\n- { \"f23\", offsetof(CPUSPARCState, fpr[11].l.lower) },\n- { \"f24\", offsetof(CPUSPARCState, fpr[12].l.upper) },\n- { \"f25\", offsetof(CPUSPARCState, fpr[12].l.lower) },\n- { \"f26\", offsetof(CPUSPARCState, fpr[13].l.upper) },\n- { \"f27\", offsetof(CPUSPARCState, fpr[13].l.lower) },\n- { \"f28\", offsetof(CPUSPARCState, fpr[14].l.upper) },\n- { \"f29\", offsetof(CPUSPARCState, fpr[14].l.lower) },\n- { \"f30\", offsetof(CPUSPARCState, fpr[15].l.upper) },\n- { \"f31\", offsetof(CPUSPARCState, fpr[15].l.lower) },\n #ifdef TARGET_SPARC64\n- { \"f32\", offsetof(CPUSPARCState, fpr[16]) },\n- { \"f34\", offsetof(CPUSPARCState, fpr[17]) },\n- { \"f36\", offsetof(CPUSPARCState, fpr[18]) },\n- { \"f38\", offsetof(CPUSPARCState, fpr[19]) },\n- { \"f40\", offsetof(CPUSPARCState, fpr[20]) },\n- { \"f42\", offsetof(CPUSPARCState, fpr[21]) },\n- { \"f44\", offsetof(CPUSPARCState, fpr[22]) },\n- { \"f46\", offsetof(CPUSPARCState, fpr[23]) },\n- { \"f48\", offsetof(CPUSPARCState, fpr[24]) },\n- { \"f50\", offsetof(CPUSPARCState, fpr[25]) },\n- { \"f52\", offsetof(CPUSPARCState, fpr[26]) },\n- { \"f54\", offsetof(CPUSPARCState, fpr[27]) },\n- { \"f56\", offsetof(CPUSPARCState, fpr[28]) },\n- { \"f58\", offsetof(CPUSPARCState, fpr[29]) },\n- { \"f60\", offsetof(CPUSPARCState, fpr[30]) },\n- { \"f62\", offsetof(CPUSPARCState, fpr[31]) },\n { \"asi\", offsetof(CPUSPARCState, asi) },\n { \"pstate\", offsetof(CPUSPARCState, pstate) },\n { \"cansave\", offsetof(CPUSPARCState, cansave) },\n@@ -154,7 +48,6 @@ const MonitorDef monitor_defs[] = {\n { \"otherwin\", offsetof(CPUSPARCState, otherwin) },\n { \"wstate\", offsetof(CPUSPARCState, wstate) },\n { \"cleanwin\", offsetof(CPUSPARCState, cleanwin) },\n- { \"fprs\", offsetof(CPUSPARCState, fprs), NULL, MD_I32 },\n #endif\n { NULL },\n };\n","prefixes":["v2","17/50"]}