{"id":2198276,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2198276/?format=json","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.0/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260219175130.2839234-7-dario.binacchi@amarulasolutions.com>","date":"2026-02-19T17:51:17","name":"[6/8] spi: stm32: add support for bits-per-word setting","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":false,"hash":"36251f52c362a876b49bd871d1bc6b204510976f","submitter":{"id":83038,"url":"http://patchwork.ozlabs.org/api/1.0/people/83038/?format=json","name":"Dario Binacchi","email":"dario.binacchi@amarulasolutions.com"},"delegate":{"id":3651,"url":"http://patchwork.ozlabs.org/api/1.0/users/3651/?format=json","username":"trini","first_name":"Tom","last_name":"Rini","email":"trini@ti.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260219175130.2839234-7-dario.binacchi@amarulasolutions.com/mbox/","series":[{"id":492708,"url":"http://patchwork.ozlabs.org/api/1.0/series/492708/?format=json","date":"2026-02-19T17:51:11","name":"video: support Rocktech RK050HR345-CT106A panel","version":1,"mbox":"http://patchwork.ozlabs.org/series/492708/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2198276/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com\n header.a=rsa-sha256 header.s=google header.b=FvjkqJIk;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)","phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=amarulasolutions.com","phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de","phobos.denx.de;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com\n header.b=\"FvjkqJIk\";\n\tdkim-atps=neutral","phobos.denx.de; dmarc=pass (p=none dis=none)\n header.from=amarulasolutions.com","phobos.denx.de; spf=pass\n smtp.mailfrom=dario.binacchi@amarulasolutions.com"],"Received":["from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fH1Dr1D7tz1xpl\n\tfor ; Fri, 20 Feb 2026 04:52:44 +1100 (AEDT)","from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id DBCCA83D0B;\n\tThu, 19 Feb 2026 18:52:17 +0100 (CET)","by phobos.denx.de (Postfix, from userid 109)\n id 8760C83D0B; Thu, 19 Feb 2026 18:52:16 +0100 (CET)","from mail-wm1-x335.google.com (mail-wm1-x335.google.com\n [IPv6:2a00:1450:4864:20::335])\n (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 8FBE983E21\n for ; Thu, 19 Feb 2026 18:52:14 +0100 (CET)","by mail-wm1-x335.google.com with SMTP id\n 5b1f17b1804b1-4836d4c26d3so11655905e9.2\n for ; Thu, 19 Feb 2026 09:52:14 -0800 (PST)","from dario-ThinkPad-P14s-Gen-5.homenet.telecomitalia.it\n (host-95-248-31-95.retail.telecomitalia.it. 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This is required for peripherals with non-standard\nrequirements, such as display panels that need 9-bit word transfers\nduring the initialization and setup phase.\n\nSigned-off-by: Dario Binacchi \n---\n\n drivers/spi/stm32_spi.c | 62 +++++++++++++++++++++++++++++++++++++----\n 1 file changed, 57 insertions(+), 5 deletions(-)","diff":"diff --git a/drivers/spi/stm32_spi.c b/drivers/spi/stm32_spi.c\nindex adba97915cd3..39ea69c68174 100644\n--- a/drivers/spi/stm32_spi.c\n+++ b/drivers/spi/stm32_spi.c\n@@ -192,6 +192,11 @@ static void stm32_spi_read_rxfifo(struct udevice *bus)\n \tlog_debug(\"%d bytes left\\n\", priv->rx_len);\n }\n \n+static bool stm32_spi_is_enabled(void __iomem *base)\n+{\n+\treturn !!(readl(base + STM32_SPI_CR1) & SPI_CR1_SPE);\n+}\n+\n static int stm32_spi_enable(void __iomem *base)\n {\n \tlog_debug(\"\\n\");\n@@ -381,6 +386,44 @@ static int stm32_spi_set_speed(struct udevice *bus, uint hz)\n \treturn 0;\n }\n \n+static int _stm32_spi_set_wordlen(struct udevice *bus, unsigned int wordlen)\n+{\n+\tstruct stm32_spi_priv *priv = dev_get_priv(bus);\n+\tstruct stm32_spi_plat *plat = dev_get_plat(bus);\n+\tvoid __iomem *base = plat->base;\n+\tbool spi_enabled;\n+\n+\tif ((wordlen - 1) < SPI_CFG1_DSIZE_MIN ||\n+\t (wordlen - 1) > SPI_CFG1_DSIZE) {\n+\t\tdev_err(bus, \"Cannot set wordlen to %u [%d - %d]\\n\",\n+\t\t\twordlen, SPI_CFG1_DSIZE_MIN + 1,\n+\t\t\tSPI_CFG1_DSIZE + 1);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tspi_enabled = stm32_spi_is_enabled(plat->base);\n+\tif (spi_enabled)\n+\t\tstm32_spi_disable(plat->base);\n+\n+\tdev_dbg(bus, \"bits_per_word=%d\\n\", wordlen);\n+\n+\tpriv->cur_bpw = wordlen;\n+\tclrsetbits_le32(base + STM32_SPI_CFG1, SPI_CFG1_DSIZE,\n+\t\t\tpriv->cur_bpw - 1);\n+\n+\tif (spi_enabled)\n+\t\tstm32_spi_enable(plat->base);\n+\n+\treturn 0;\n+}\n+\n+static int stm32_spi_set_wordlen(struct udevice *slave, unsigned int wordlen)\n+{\n+\tstruct udevice *bus = dev_get_parent(slave);\n+\n+\treturn _stm32_spi_set_wordlen(bus, wordlen);\n+}\n+\n static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen,\n \t\t\t const void *dout, void *din, unsigned long flags)\n {\n@@ -394,11 +437,19 @@ static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen,\n \tu32 xferlen;\n \tu32 mode;\n \tint xfer_status = 0;\n+\tint nb_words;\n \n \txferlen = bitlen / 8;\n \n-\tif (xferlen <= SPI_CR2_TSIZE)\n-\t\twritel(xferlen, base + STM32_SPI_CR2);\n+\tif (priv->cur_bpw <= 8)\n+\t\tnb_words = xferlen;\n+\telse if (priv->cur_bpw <= 16)\n+\t\tnb_words = DIV_ROUND_UP(xferlen * 8, 16);\n+\telse\n+\t\tnb_words = DIV_ROUND_UP(xferlen * 8, 32);\n+\n+\tif (nb_words <= SPI_CR2_TSIZE)\n+\t\twritel(nb_words, base + STM32_SPI_CR2);\n \telse\n \t\treturn -EMSGSIZE;\n \n@@ -406,6 +457,8 @@ static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen,\n \tpriv->rx_buf = din;\n \tpriv->tx_len = priv->tx_buf ? xferlen : 0;\n \tpriv->rx_len = priv->rx_buf ? xferlen : 0;\n+\tdev_dbg(bus, \"bitlen: %d, xferlen: %d, nb_words: %d\\n\",\n+\t\tbitlen, xferlen, nb_words);\n \n \tmode = SPI_FULL_DUPLEX;\n \tif (!priv->tx_buf)\n@@ -567,9 +620,7 @@ static int stm32_spi_probe(struct udevice *dev)\n \tpriv->fifo_size = stm32_spi_get_fifo_size(dev);\n \tpriv->cur_mode = SPI_FULL_DUPLEX;\n \tpriv->cur_xferlen = 0;\n-\tpriv->cur_bpw = SPI_DEFAULT_WORDLEN;\n-\tclrsetbits_le32(base + STM32_SPI_CFG1, SPI_CFG1_DSIZE,\n-\t\t\tpriv->cur_bpw - 1);\n+\t_stm32_spi_set_wordlen(dev, SPI_DEFAULT_WORDLEN);\n \n \tfor (i = 0; i < ARRAY_SIZE(plat->cs_gpios); i++) {\n \t\tif (!dm_gpio_is_valid(&plat->cs_gpios[i]))\n@@ -630,6 +681,7 @@ static const struct dm_spi_ops stm32_spi_ops = {\n \t.release_bus\t= stm32_spi_release_bus,\n \t.set_mode\t= stm32_spi_set_mode,\n \t.set_speed\t= stm32_spi_set_speed,\n+\t.set_wordlen = stm32_spi_set_wordlen,\n \t.xfer\t\t= stm32_spi_xfer,\n };\n \n","prefixes":["6/8"]}