{"id":2198267,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2198267/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260219171810.602667-13-alex.bennee@linaro.org>","date":"2026-02-19T17:18:08","name":"[RFC,v2,12/14] hw/alpha: add a reset function for the clipper machine","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"f14d8ef79565b48735c307db4fc5f704eaf41e74","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/1.0/people/39532/?format=json","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260219171810.602667-13-alex.bennee@linaro.org/mbox/","series":[{"id":492705,"url":"http://patchwork.ozlabs.org/api/1.0/series/492705/?format=json","date":"2026-02-19T17:17:57","name":"cpu_reset clean-ups for arm, alpha, mips, m68k and tricore","version":2,"mbox":"http://patchwork.ozlabs.org/series/492705/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2198267/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=D+mOLxD3;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::532;\n envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x532.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Once this is setup we can move CPU reset to a 3-phase reset handler.\n\nSigned-off-by: Alex Bennée \n---\n hw/alpha/dp264.c | 10 ++++++++++\n 1 file changed, 10 insertions(+)","diff":"diff --git a/hw/alpha/dp264.c b/hw/alpha/dp264.c\nindex 98219f04569..f660fc41bcd 100644\n--- a/hw/alpha/dp264.c\n+++ b/hw/alpha/dp264.c\n@@ -17,6 +17,7 @@\n #include \"hw/ide/pci.h\"\n #include \"hw/isa/superio.h\"\n #include \"qemu/datadir.h\"\n+#include \"system/reset.h\"\n \n static uint64_t cpu_alpha_superpage_to_phys(void *opaque, uint64_t addr)\n {\n@@ -42,6 +43,14 @@ static int clipper_pci_map_irq(PCIDevice *d, int irq_num)\n return (slot + 1) * 4 + irq_num;\n }\n \n+static void clipper_reset(MachineState *ms, ResetType type)\n+{\n+ CPUState *cs = first_cpu;\n+\n+ qemu_devices_reset(type);\n+ cpu_reset(cs);\n+}\n+\n static void clipper_init(MachineState *machine)\n {\n ram_addr_t ram_size = machine->ram_size;\n@@ -205,6 +214,7 @@ static void clipper_machine_init(MachineClass *mc)\n {\n mc->desc = \"Alpha DP264/CLIPPER\";\n mc->init = clipper_init;\n+ mc->reset = clipper_reset;\n mc->block_default_type = IF_IDE;\n mc->max_cpus = 4;\n mc->is_default = true;\n","prefixes":["RFC","v2","12/14"]}