{"id":2198258,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2198258/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260219171810.602667-9-alex.bennee@linaro.org>","date":"2026-02-19T17:18:04","name":"[RFC,v2,08/14] hw/mips: drop cpu_reset in mips_cpu_realizefn","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"32b04a2a1e700bf80303ae554fbf94ce25a37c69","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/1.0/people/39532/?format=json","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260219171810.602667-9-alex.bennee@linaro.org/mbox/","series":[{"id":492705,"url":"http://patchwork.ozlabs.org/api/1.0/series/492705/?format=json","date":"2026-02-19T17:17:57","name":"cpu_reset clean-ups for arm, alpha, mips, m68k and tricore","version":2,"mbox":"http://patchwork.ozlabs.org/series/492705/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2198258/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Fq78MWP7;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::535;\n envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x535.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"We will always do a cpu_reset during mips_cpu_reset_hold().\n\nMessage-ID: <20260108143423.1378674-10-alex.bennee@linaro.org>\nSigned-off-by: Alex Bennée \n---\n target/mips/cpu.c | 1 -\n 1 file changed, 1 deletion(-)","diff":"diff --git a/target/mips/cpu.c b/target/mips/cpu.c\nindex e424d115018..f20613f1223 100644\n--- a/target/mips/cpu.c\n+++ b/target/mips/cpu.c\n@@ -488,7 +488,6 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp)\n fpu_init(env, env->cpu_model);\n mvp_init(env);\n \n- cpu_reset(cs);\n qemu_init_vcpu(cs);\n \n mcc->parent_realize(dev, errp);\n","prefixes":["RFC","v2","08/14"]}