{"id":2198223,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2198223/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260219144901.3317747-4-ruslichenko.r@gmail.com>","date":"2026-02-19T14:48:50","name":"[v2,22/33] hw/intc/arm_gic: implement FDT_GENERIC_INTC and fdt support","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"b8e4adb2c1b856862c818a0476e7bfe81c1e0937","submitter":{"id":92275,"url":"http://patchwork.ozlabs.org/api/1.0/people/92275/?format=json","name":"Ruslan Ruslichenko","email":"ruslichenko.r@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260219144901.3317747-4-ruslichenko.r@gmail.com/mbox/","series":[{"id":492690,"url":"http://patchwork.ozlabs.org/api/1.0/series/492690/?format=json","date":"2026-02-19T14:33:04","name":"hw/arm: Introduce generic FDT-driven machine","version":2,"mbox":"http://patchwork.ozlabs.org/series/492690/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2198223/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=PI1DRAsc;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fGxFT6ZVKz1xpl\n\tfor ; Fri, 20 Feb 2026 01:53:01 +1100 (AEDT)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1vt5MM-00043E-3U; Thu, 19 Feb 2026 09:50:30 -0500","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1vt5Lt-0003lV-Fu\n for qemu-devel@nongnu.org; Thu, 19 Feb 2026 09:50:11 -0500","from mail-wr1-x432.google.com ([2a00:1450:4864:20::432])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1vt5Ln-00083i-HT\n for qemu-devel@nongnu.org; Thu, 19 Feb 2026 09:49:58 -0500","by mail-wr1-x432.google.com with SMTP id\n ffacd0b85a97d-4359108fd24so668892f8f.2\n for ; Thu, 19 Feb 2026 06:49:45 -0800 (PST)","from thinkpad-t470s.. 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Iglesias\" ,\n Ruslan_Ruslichenko@epam.com, balaton@eik.bme.hu","Subject":"[PATCH v2 22/33] hw/intc/arm_gic: implement FDT_GENERIC_INTC and fdt\n support","Date":"Thu, 19 Feb 2026 15:48:50 +0100","Message-ID":"<20260219144901.3317747-4-ruslichenko.r@gmail.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260219144901.3317747-1-ruslichenko.r@gmail.com>","References":"<20260219143332.3316679-1-ruslichenko.r@gmail.com>\n <20260219144901.3317747-1-ruslichenko.r@gmail.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::432;\n envelope-from=ruslichenko.r@gmail.com; helo=mail-wr1-x432.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Ruslan Ruslichenko \n\nThe patch implements TYPE_FDT_GENERIC_INTC interface, which\nenables GIC to be instantiated and wired via the device tree\ndescription.\n\nThe implemented interface method are following:\n1. 'get_irq': Parses device tree interrupt specifiers\nand return correct qemu_irq for devices which has IRQ's wired\nto GIC.\n2. 'auto_parent': Automatically connect the GIC's output signals\nto the CPU's found in current machine configuration.\n\nSigned-off-by: Ruslan Ruslichenko \n---\n hw/intc/arm_gic.c | 32 +++++++++++++++++++++++++\n hw/intc/arm_gic_common.c | 50 ++++++++++++++++++++++++++++++++++++++++\n 2 files changed, 82 insertions(+)","diff":"diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c\nindex 4d4b79e6f3..2be44d8e5b 100644\n--- a/hw/intc/arm_gic.c\n+++ b/hw/intc/arm_gic.c\n@@ -24,12 +24,15 @@\n #include \"gic_internal.h\"\n #include \"qapi/error.h\"\n #include \"hw/core/cpu.h\"\n+#include \"hw/core/boards.h\"\n #include \"qemu/log.h\"\n #include \"qemu/module.h\"\n #include \"trace.h\"\n #include \"system/kvm.h\"\n #include \"system/qtest.h\"\n \n+#include \"hw/core/fdt_generic_util.h\"\n+\n /* #define DEBUG_GIC */\n \n #ifdef DEBUG_GIC\n@@ -2162,12 +2165,41 @@ static void arm_gic_realize(DeviceState *dev, Error **errp)\n \n }\n \n+static void arm_gic_fdt_auto_parent(FDTGenericIntc *obj, Error **errp)\n+{\n+ GICState *s = ARM_GIC(obj);\n+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);\n+ int num_cpus = current_machine->smp.cpus;\n+ CPUState *cs;\n+ int i = 0;\n+\n+ for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {\n+ if (i >= s->num_cpu) {\n+ break;\n+ }\n+\n+ sysbus_connect_irq(sbd, i,\n+ qdev_get_gpio_in(DEVICE(cs), 0));\n+ sysbus_connect_irq(sbd, i + num_cpus,\n+ qdev_get_gpio_in(DEVICE(cs), 1));\n+ sysbus_connect_irq(sbd, i + 2 * num_cpus,\n+ qdev_get_gpio_in(DEVICE(cs), 2));\n+ sysbus_connect_irq(sbd, i + 3 * num_cpus,\n+ qdev_get_gpio_in(DEVICE(cs), 3));\n+ i++;\n+ }\n+\n+ /* FIXME: Add some error checking */\n+}\n+\n static void arm_gic_class_init(ObjectClass *klass, const void *data)\n {\n DeviceClass *dc = DEVICE_CLASS(klass);\n ARMGICClass *agc = ARM_GIC_CLASS(klass);\n+ FDTGenericIntcClass *fgic = FDT_GENERIC_INTC_CLASS(klass);\n \n device_class_set_parent_realize(dc, arm_gic_realize, &agc->parent_realize);\n+ fgic->auto_parent = arm_gic_fdt_auto_parent;\n }\n \n static const TypeInfo arm_gic_info = {\ndiff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c\nindex 304d89cf56..04787cff79 100644\n--- a/hw/intc/arm_gic_common.c\n+++ b/hw/intc/arm_gic_common.c\n@@ -28,6 +28,8 @@\n #include \"migration/vmstate.h\"\n #include \"system/kvm.h\"\n \n+#include \"hw/core/fdt_generic_util.h\"\n+\n static int gic_pre_save(void *opaque)\n {\n GICState *s = (GICState *)opaque;\n@@ -348,6 +350,51 @@ static void arm_gic_common_linux_init(ARMLinuxBootIf *obj,\n }\n }\n \n+static int arm_gic_common_fdt_get_irq(FDTGenericIntc *obj, qemu_irq *irqs,\n+ uint32_t *cells, int ncells, int max,\n+ Error **errp)\n+{\n+ GICState *gs = ARM_GIC_COMMON(obj);\n+ int cpu = 0;\n+ uint32_t idx;\n+\n+ if (ncells != 3) {\n+ error_setg(errp, \"ARM GIC requires 3 interrupt cells, %d cells given\",\n+ ncells);\n+ return 0;\n+ }\n+ idx = cells[1];\n+\n+ switch (cells[0]) {\n+ case 0:\n+ if (idx >= gs->num_irq) {\n+ error_setg(errp, \"ARM GIC SPI has maximum index of %\" PRId32 \", \"\n+ \"index %\" PRId32 \" given\", gs->num_irq - 1, idx);\n+ return 0;\n+ }\n+ (*irqs) = qdev_get_gpio_in(DEVICE(obj), cells[1]);\n+ return 1;\n+ case 1: /* PPI */\n+ if (idx >= 16) {\n+ error_setg(errp, \"ARM GIC PPI has maximum index of 15, \"\n+ \"index %\" PRId32 \" given\", idx);\n+ return 0;\n+ }\n+ for (cpu = 0; cpu < max && cpu < gs->num_cpu; cpu++) {\n+ if (cells[2] & 1 << (cpu + 8)) {\n+ *irqs = qdev_get_gpio_in(DEVICE(obj),\n+ gs->num_irq - 16 + idx + cpu * 32);\n+ }\n+ irqs++;\n+ }\n+ return cpu;\n+ default:\n+ error_setg(errp, \"Invalid cell 0 value in interrupt binding: %d\",\n+ cells[0]);\n+ return 0;\n+ }\n+}\n+\n static const Property arm_gic_common_properties[] = {\n DEFINE_PROP_UINT32(\"num-cpu\", GICState, num_cpu, 1),\n DEFINE_PROP_UINT32(\"first-cpu-index\", GICState, first_cpu_index, 0),\n@@ -368,12 +415,14 @@ static void arm_gic_common_class_init(ObjectClass *klass, const void *data)\n DeviceClass *dc = DEVICE_CLASS(klass);\n ResettableClass *rc = RESETTABLE_CLASS(klass);\n ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass);\n+ FDTGenericIntcClass *fgic = FDT_GENERIC_INTC_CLASS(klass);\n \n rc->phases.hold = arm_gic_common_reset_hold;\n dc->realize = arm_gic_common_realize;\n device_class_set_props(dc, arm_gic_common_properties);\n dc->vmsd = &vmstate_gic;\n albifc->arm_linux_init = arm_gic_common_linux_init;\n+ fgic->get_irq = arm_gic_common_fdt_get_irq;\n }\n \n static const TypeInfo arm_gic_common_type = {\n@@ -385,6 +434,7 @@ static const TypeInfo arm_gic_common_type = {\n .abstract = true,\n .interfaces = (const InterfaceInfo[]) {\n { TYPE_ARM_LINUX_BOOT_IF },\n+ { TYPE_FDT_GENERIC_INTC },\n { },\n },\n };\n","prefixes":["v2","22/33"]}