{"id":2198177,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2198177/?format=json","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/1.0/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"","date":"2026-02-19T14:02:04","name":"[v2,3/7,Vectorizer,Aarch64] : SLP MATCH Pattern: Add implementation for match / nmatch SVE instructions","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"a7bf6037b5dd3778508eda82152df17e88fbffb0","submitter":{"id":92460,"url":"http://patchwork.ozlabs.org/api/1.0/people/92460/?format=json","name":"Andrei Tirziu via Sourceware Forge","email":"forge-bot+why@forge-stage.sourceware.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/bmm.hfy4c1w8xq.gcc.gcc-TEST.why.135.2.3@forge-stage.sourceware.org/mbox/","series":[{"id":492684,"url":"http://patchwork.ozlabs.org/api/1.0/series/492684/?format=json","date":"2026-02-19T14:02:02","name":"Vectorizer: New SLP Pattern","version":2,"mbox":"http://patchwork.ozlabs.org/series/492684/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2198177/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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server2.sourceware.org","From":"Andrei Tirziu via Sourceware Forge\n ","Date":"Thu, 19 Feb 2026 14:02:04 +0000","Subject":"[PATCH v2 3/7] [Vectorizer][Aarch64]: SLP MATCH Pattern: Add\n implementation for match / nmatch SVE instructions","To":"gcc-patches mailing list ","Cc":"Tamar Christina ,\n Victor Do Nascimento ","Message-ID":"\n ","X-Mailer":"batrachomyomachia","X-Pull-Request-Organization":"gcc","X-Pull-Request-Repository":"gcc-TEST","X-Pull-Request":"https://forge.sourceware.org/gcc/gcc-TEST/pulls/135","References":"\n ","In-Reply-To":"\n ","X-Patch-URL":"\n https://forge.sourceware.org/why/gcc/commit/d5cec2a1672e0b22de93658c4dc33f00210270ad","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Reply-To":"gcc-patches mailing list ,\n Tamar Christina ,\n Victor Do Nascimento ,\n andreinichita.tirziu@arm.com","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"From: Andrei Nichita Tirziu \n\nThe optabs introduced for the new MATCH Pattern need an implementation\nin the backend so that the vectorizer can complete the transformation.\n\nThe non-conditional optab is expanded to its conditional counterpart,\nusing an all-true predicate as a mask.\nThe conditional optab emits an SVE `match` or `nmatch` instructions.\n\nThe SVE backend doesn't make use of the `len` or `bias` arguments that\nthe conditional-len optab has, so there is no need to implement\nsuch a version.\n\ngcc/ChangeLog:\n\n\t* config/aarch64/aarch64-sve2.md: New patterns for match,\n\t\t\t\t\t nmatch optabs.\n\t* config/aarch64/iterators.md: New iterator for MATCH,\n\t\t\t\t NMATCH modes.\n---\n gcc/config/aarch64/aarch64-sve2.md | 70 ++++++++++++++++++++++++++++++\n gcc/config/aarch64/iterators.md | 3 ++\n 2 files changed, 73 insertions(+)","diff":"diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md\nindex 4a2d2c1cb8ce..089216533625 100644\n--- a/gcc/config/aarch64/aarch64-sve2.md\n+++ b/gcc/config/aarch64/aarch64-sve2.md\n@@ -4333,6 +4333,76 @@\n ;; - NMATCH\n ;; -------------------------------------------------------------------------\n \n+;; SVE MATCH instruction. This is used by the `vec_match_any_from_optab`.\n+;;\n+;; The initial operands are (result, variants_vector, invariants_vector).\n+;; A full-true mask is generated to transform it into a valid instruction.\n+(define_expand \"@vec_match_any_from_\"\n+ [(set (match_operand: 0 \"register_operand\" \"=Upa\")\n+\t(unspec:\n+\t [(match_operand:SVE_MATCH_AND_NMATCH 1 \"register_operand\" \"w\")\n+\t (match_operand:SVE_MATCH_AND_NMATCH 2 \"register_operand\" \"w\")]\n+\t UNSPEC_MATCH))]\n+ \"TARGET_SVE2 && TARGET_NON_STREAMING\"\n+ {\n+ rtx true_pred = aarch64_ptrue_reg (mode);\n+ emit_insn (gen_vec_match_any_from_cond_\n+\t (operands[0], operands[1], operands[2], true_pred, operands[1]));\n+ DONE;\n+ }\n+)\n+\n+;; SVE MATCH instruction. This is used by the `cond_vec_match_any_from_optab`.\n+;;\n+;; The operands are\n+;; (result, variants_vector, invariants_vector, mask, ignored_vector).\n+(define_insn \"@vec_match_any_from_cond_\"\n+ [(set (match_operand: 0 \"register_operand\" \"=Upa\")\n+\t(unspec:\n+\t [(match_operand:SVE_MATCH_AND_NMATCH 1 \"register_operand\" \"w\")\n+\t (match_operand:SVE_MATCH_AND_NMATCH 2 \"register_operand\" \"w\")\n+\t (match_operand: 3 \"register_operand\" \"Upa\")\n+\t (match_operand:SVE_MATCH_AND_NMATCH 4 \"register_operand\" \"w\")]\n+\t UNSPEC_MATCH))]\n+ \"TARGET_SVE2 && TARGET_NON_STREAMING\"\n+ \"match\\t%0., %3/z, %1., %2.\"\n+)\n+\n+;; SVE NMATCH instruction. This is used by the `vec_match_none_from_optab`.\n+;;\n+;; The initial operands are (result, variants_vector, invariants_vector).\n+;; A full-true mask is generated to transform it into a valid instruction.\n+(define_expand \"@vec_match_none_from_\"\n+ [(set (match_operand: 0 \"register_operand\" \"=Upa\")\n+\t(unspec:\n+\t [(match_operand:SVE_MATCH_AND_NMATCH 1 \"register_operand\" \"w\")\n+\t (match_operand:SVE_MATCH_AND_NMATCH 2 \"register_operand\" \"w\")]\n+\t UNSPEC_NMATCH))]\n+ \"TARGET_SVE2 && TARGET_NON_STREAMING\"\n+ {\n+ rtx true_pred = aarch64_ptrue_reg (mode);\n+ emit_insn (gen_vec_match_none_from_cond_\n+\t (operands[0], operands[1], operands[2], true_pred, operands[1]));\n+ DONE;\n+ }\n+)\n+\n+;; SVE NMATCH instruction. This is used by the `cond_vec_match_none_from_optab`.\n+;;\n+;; The operands are\n+;; (result, variants_vector, invariants_vector, mask, ignored_vector).\n+(define_insn \"@vec_match_none_from_cond_\"\n+ [(set (match_operand: 0 \"register_operand\" \"=Upa\")\n+\t(unspec:\n+\t [(match_operand:SVE_MATCH_AND_NMATCH 1 \"register_operand\" \"w\")\n+\t (match_operand:SVE_MATCH_AND_NMATCH 2 \"register_operand\" \"w\")\n+\t (match_operand: 3 \"register_operand\" \"Upa\")\n+\t (match_operand:SVE_MATCH_AND_NMATCH 4 \"register_operand\" \"w\")]\n+\t UNSPEC_NMATCH))]\n+ \"TARGET_SVE2 && TARGET_NON_STREAMING\"\n+ \"nmatch\\t%0., %3/z, %1., %2.\"\n+)\n+\n ;; Predicated string matching.\n (define_insn \"@aarch64_pred_\"\n [(set (match_operand: 0 \"register_operand\")\ndiff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md\nindex b425b0ed2ca3..d5c3073f153c 100644\n--- a/gcc/config/aarch64/iterators.md\n+++ b/gcc/config/aarch64/iterators.md\n@@ -723,6 +723,9 @@\n ;; Used for narrowing SVE floating point operations.\n (define_mode_iterator VNx16F_NARROW [SVE_FULL_HFx2 VNx16SF])\n \n+;; SVE modes supported by MATCH and NMATCH instructions.\n+(define_mode_iterator SVE_MATCH_AND_NMATCH [VNx16QI VNx8HI])\n+\n ;; All SVE predicate modes.\n (define_mode_iterator PRED_ALL [VNx16BI VNx8BI VNx4BI VNx2BI])\n \n","prefixes":["v2","3/7","Vectorizer","Aarch64"]}