{"id":2198175,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2198175/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260219054207.471303-6-manali.shukla@amd.com>","date":"2026-02-19T05:42:04","name":"[v1,5/8] i386/kvm: Add extended LAPIC capability negotiation","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"545b7017bfc0303bcdb97482336cfdde472d4bd5","submitter":{"id":90099,"url":"http://patchwork.ozlabs.org/api/1.0/people/90099/?format=json","name":"Manali Shukla","email":"manali.shukla@amd.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260219054207.471303-6-manali.shukla@amd.com/mbox/","series":[{"id":492683,"url":"http://patchwork.ozlabs.org/api/1.0/series/492683/?format=json","date":"2026-02-19T05:42:03","name":"i386/kvm: Add support for extended APIC register space","version":1,"mbox":"http://patchwork.ozlabs.org/series/492683/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2198175/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=amd.com header.i=@amd.com header.a=rsa-sha256\n header.s=selector1 header.b=HutOtLXZ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=satlexmb07.amd.com; pr=C","permerror client-ip=2a01:111:f403:c001::2;\n envelope-from=Manali.Shukla@amd.com;\n helo=SJ2PR03CU001.outbound.protection.outlook.com"],"From":"Manali Shukla ","To":"","CC":"Cornelia Huck , Eduardo Habkost ,\n , Marcel Apfelbaum ,\n \"Marcelo Tosatti\" , \"Michael S . Tsirkin\"\n , \"Paolo Bonzini\" , Sean Christopherson\n , Richard Henderson , Naveen\n N Rao , Nikunj Dadhaniya ,\n ","Subject":"[PATCH v1 5/8] i386/kvm: Add extended LAPIC capability negotiation","Date":"Thu, 19 Feb 2026 05:42:04 +0000","Message-ID":"<20260219054207.471303-6-manali.shukla@amd.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260219054207.471303-1-manali.shukla@amd.com>","References":"<20260219054207.471303-1-manali.shukla@amd.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-Originating-IP":"[10.180.168.240]","X-ClientProxiedBy":"satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com\n (10.181.42.216)","X-EOPAttributedMessage":"0","X-MS-PublicTrafficType":"Email","X-MS-TrafficTypeDiagnostic":"SJ1PEPF00001CDC:EE_|BN3PR12MB9593:EE_","X-MS-Office365-Filtering-Correlation-Id":"2c23b9ed-5e0b-48f9-7394-08de6f79d44a","X-MS-Exchange-SenderADCheck":"1","X-MS-Exchange-AntiSpam-Relay":"0","X-Microsoft-Antispam":"BCL:0;\n ARA:13230040|36860700013|82310400026|7416014|376014|1800799024;","X-Microsoft-Antispam-Message-Info":"\n wAVn2Q75vuEB3PfmhLT1E0Gw07ps85Dy0cor4/br+gM9GWEl0WZVzbM54QY/UbjL9AR1nC/tK6l4IdtfexUBXweBoe2YVJ+9S/55fLcfC8zEGe8o8LTg/UuKBWxbTMxYTBtDkRrasl+IK3eRyZ/J5LDfwZv70jqgT3zFE22PdaS1OgTDfMKYus8mpbIW4qbmflLTAAhNNCQMS6yzOXMljh9PTcu8+kex07bf+X2ajPCA8aMlESMgvr+APjzBWLqHzHbsnqA68vtDOxeSYTl28F4lYG9jzvS2kchorp+9YQCiZo9Fy5CV1/0wWGQAhwlxVm+u8xZF4xq2sOlEglwO5HBq1cBMXDR7gCo3bA8c3pZ1q4H/e+BquuFikhZlmr/R+U20pdLYY0N3c9JfutvWuaL6LfZjeo++OyexxYxqmHMNTs6uReRBhAK/qliQ35RXozEkJrC6zkuZbYHDiHBq0+G+G1HM9B9MCuZE+Mk1xw9s1q/gS6eIYLtdHkone2nv/JTcsqpSIJdcQ07UbdXdYzUtRoyu4NnJNGijFDenbhoFX1Ck+qDGb0DEmJvumAE1wpk7O3bZfU14dQLxfTpzxoWUf6aA8aveXXgxXhSWlr1NGk3X/nJcwNyr9fD4Ddd1LoM1k6qc0t5XHI3Toi4199wYL7sfXE96KanO+IpfBxX9M7Gzutq9CagB/GS3wJj8HLmKXL1DfMVcrOHEkSw3YryuAzjPe4Manj15Ch6uEGE3xf0vMa7Csxo0sGkPVw8YevjyWFEJliiI8jL0PzhjphP+diCjmEOoVcDE4oFAuP2THg5dsaQmMSTbbFM4aL+sSnQizn3Pf+mdr+hTsAXcUen843F6br2PnAtkapxt+zZ5fzs+aCMTY8m51rdZPHdmDAHdVX1VgpN0nWmn3RPxSwFenjq6LaWUeOh0MRCp+tVM/kmBK9EJk0S+WByzl5pX9vcKNE6P31FJG6sF+lJNRfENg4s1ATIBAonxuz08CwAVoJ6glbbuk7Ig/yUDa0NCJQS24+5+z54XBu9INA8KKJeWrUtzEetkGMqfujzbKU0JERHzqqixjV46gXImgCGK9SSXqT/5K+e32gdAIUaDWbfIbTEgaKD7Mgtssbql9U0aOMNKjLYlEcZ2bQVMwPmuyEcOb4wvOKH11/7Hm0jNCwxGEvZs+E8/n0qB2nQe7eLvVsOXOTwSLd0xWTLqCv9mW2QpT00MMb6o1/nNAMQudegrpMTV2NSaTluS+aISbVCx1r0+bARpQ3GIG5WdNVt/Bzf49W+jWlSWju/52cZxMSmO/uPYycgL2hDhtgHdT8PMQd5RlxBJl8/dPmU1pPKrLZMmEYpUbhdHaz/FypRm8mHCnQLib/+jT/zFQ2+mlT1M8OCnxzRvQXXiAdtq7v9riFaMd2rPFBHBURg3QVrNWYIHtlVAhWwnwuCBCel63hPj02z+sA+b/8UUDGOLB1XJJXoteEdEtnyamlmNyfFoDDPW2QZiy8iJyeoDV+P79rT6mB48Qgxrc7cH7CjuexjSWffb0/sIwc8WJEeEtBGCUfEB+qnnPbCwbdHGgAx1T7lJNKK1G0y1fcKJMF+01KaziJz2hon8+zY2MUuvKADEiGMBRAUqmUScca3d9UyqVTH/G7pfRAfFVmdC2F6AtzajufUEOOCf2+0gc7/anF9DWw==","X-Forefront-Antispam-Report":"CIP:165.204.84.17; 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Ip=[165.204.84.17];\n Helo=[satlexmb07.amd.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n SJ1PEPF00001CDC.namprd05.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"BN3PR12MB9593","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.043,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-Mailman-Approved-At":"Thu, 19 Feb 2026 08:55:34 -0500","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Negotiate KVM_CAP_LAPIC2 during vCPU pre-creation. Enable\nKVM_LAPIC2_DEFAULT for the 4KB APIC page. If the CPU has\nExtApicSpace (arch_has_extapic()), also enable KVM_LAPIC2_AMD_DEFAULT\nand use the intersection of what host and guest support.\n\nUse a VM-wide has_lapic2 flag so the capability is enabled once on the\nfirst vCPU and reused for the rest. When extended APIC is supported on\nboth host and guest, set has_extapic for use when syncing extended APIC\nregisters with KVM. Allocate extended LVT state in\nkvm_initialize_extlvt() during pre-creation and free it in\nkvm_uninitialize_extlvt() on vCPU destroy.\n\nSuggested-by: Naveen N Rao (AMD) \nSigned-off-by: Manali Shukla \n---\n target/i386/kvm/kvm.c | 61 +++++++++++++++++++++++++++++++++++++-\n target/i386/kvm/kvm_i386.h | 2 ++\n 2 files changed, 62 insertions(+), 1 deletion(-)","diff":"diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c\nindex ea22aa7180..c9f4cb6430 100644\n--- a/target/i386/kvm/kvm.c\n+++ b/target/i386/kvm/kvm.c\n@@ -177,6 +177,8 @@ static int has_exception_payload;\n static int has_triple_fault_event;\n \n static bool has_msr_mcg_ext_ctl;\n+static bool has_lapic2;\n+static bool has_extapic;\n \n static struct kvm_cpuid2 *cpuid_cache;\n static struct kvm_cpuid2 *hv_cpuid_cache;\n@@ -2064,13 +2066,69 @@ full:\n abort();\n }\n \n+bool kvm_has_lapic2(void)\n+{\n+ return has_lapic2;\n+}\n+\n+bool kvm_has_extapic(void)\n+{\n+ return has_extapic;\n+}\n+\n+static int kvm_enable_extapic(X86CPU *cpu)\n+{\n+ KVMState *s = KVM_STATE(current_accel());\n+ uint64_t kvm_cap, vm_cap, final_cap;\n+ uint8_t nr_extlvt = 0;\n+ int ret;\n+\n+ if (!s) {\n+ error_report(\"KVM accelerator is not available\");\n+ return -ENODEV;\n+ }\n+\n+ if (!has_lapic2) {\n+ kvm_cap = kvm_check_extension(s, KVM_CAP_LAPIC2);\n+ if (!kvm_cap) {\n+ return 0;\n+ }\n+\n+ vm_cap = KVM_LAPIC2_DEFAULT;\n+ if (arch_has_extapic(cpu)) {\n+ vm_cap |= KVM_LAPIC2_AMD_DEFAULT;\n+ }\n+\n+ final_cap = kvm_cap & vm_cap;\n+ ret = kvm_vm_enable_cap(s, KVM_CAP_LAPIC2, 0, final_cap);\n+\n+ if (ret < 0) {\n+ error_report(\"kvm: Failed to enable EXTAPIC\");\n+ return -ENOTSUP;\n+ }\n+\n+ has_lapic2 = true;\n+ if (final_cap & KVM_LAPIC2_AMD_DEFAULT) {\n+ nr_extlvt = KVM_X86_NR_EXTLVT_DEFAULT;\n+ has_extapic = true;\n+ }\n+ }\n+\n+ if (nr_extlvt > 0) {\n+ kvm_initialize_extlvt(cpu, nr_extlvt);\n+ }\n+ return 0;\n+}\n+\n int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp)\n {\n if (is_tdx_vm()) {\n return tdx_pre_create_vcpu(cpu, errp);\n }\n \n- return 0;\n+ X86CPU *cs = X86_CPU(cpu);\n+\n+ return kvm_enable_extapic(cs);\n }\n \n int kvm_arch_init_vcpu(CPUState *cs)\n@@ -2399,6 +2457,7 @@ int kvm_arch_destroy_vcpu(CPUState *cs)\n g_free(env->nested_state);\n env->nested_state = NULL;\n \n+ kvm_uninitialize_extlvt(cpu);\n qemu_del_vm_change_state_handler(cpu->vmsentry);\n \n return 0;\ndiff --git a/target/i386/kvm/kvm_i386.h b/target/i386/kvm/kvm_i386.h\nindex 338433eb52..b28fed69d8 100644\n--- a/target/i386/kvm/kvm_i386.h\n+++ b/target/i386/kvm/kvm_i386.h\n@@ -25,6 +25,8 @@\n (kvm_irqchip_in_kernel() && !kvm_irqchip_is_split())\n \n bool kvm_has_smm(void);\n+bool kvm_has_extapic(void);\n+bool kvm_has_lapic2(void);\n bool kvm_enable_x2apic(void);\n bool kvm_hv_vpindex_settable(void);\n bool kvm_enable_hypercall(uint64_t enable_mask);\n","prefixes":["v1","5/8"]}