{"id":2198171,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2198171/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260219054207.471303-2-manali.shukla@amd.com>","date":"2026-02-19T05:42:00","name":"[v1,1/8] i386/kvm: Refactor APIC state functions to use generic register pointer","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"7a35f03f93b08eeb56531b7c2396c53e24e25140","submitter":{"id":90099,"url":"http://patchwork.ozlabs.org/api/1.0/people/90099/?format=json","name":"Manali Shukla","email":"manali.shukla@amd.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260219054207.471303-2-manali.shukla@amd.com/mbox/","series":[{"id":492683,"url":"http://patchwork.ozlabs.org/api/1.0/series/492683/?format=json","date":"2026-02-19T05:42:03","name":"i386/kvm: Add support for extended APIC register space","version":1,"mbox":"http://patchwork.ozlabs.org/series/492683/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2198171/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=amd.com header.i=@amd.com header.a=rsa-sha256\n header.s=selector1 header.b=o1G/bsIV;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=satlexmb07.amd.com; pr=C","permerror client-ip=52.101.62.48;\n envelope-from=Manali.Shukla@amd.com;\n helo=DM5PR21CU001.outbound.protection.outlook.com"],"From":"Manali Shukla ","To":"","CC":"Cornelia Huck , Eduardo Habkost ,\n , Marcel Apfelbaum ,\n \"Marcelo Tosatti\" , \"Michael S . Tsirkin\"\n , \"Paolo Bonzini\" , Sean Christopherson\n , Richard Henderson , Naveen\n N Rao , Nikunj Dadhaniya ,\n ","Subject":"[PATCH v1 1/8] i386/kvm: Refactor APIC state functions to use generic\n register pointer","Date":"Thu, 19 Feb 2026 05:42:00 +0000","Message-ID":"<20260219054207.471303-2-manali.shukla@amd.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260219054207.471303-1-manali.shukla@amd.com>","References":"<20260219054207.471303-1-manali.shukla@amd.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-Originating-IP":"[10.180.168.240]","X-ClientProxiedBy":"satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com\n (10.181.42.216)","X-EOPAttributedMessage":"0","X-MS-PublicTrafficType":"Email","X-MS-TrafficTypeDiagnostic":"SJ1PEPF00001CDF:EE_|BY5PR12MB4196:EE_","X-MS-Office365-Filtering-Correlation-Id":"e2baf6b0-36ee-4d8a-2506-08de6f79cb5c","X-MS-Exchange-SenderADCheck":"1","X-MS-Exchange-AntiSpam-Relay":"0","X-Microsoft-Antispam":"BCL:0;\n ARA:13230040|82310400026|376014|7416014|36860700013|1800799024;","X-Microsoft-Antispam-Message-Info":"\n jgXeXdNd7hHTSpWAVBOGfvjewd0m3ehDTLJFkHNaHd4yocFqtIqRUClJP0MeSrjreG298mH+EKBZXj3W0fgZypk1L4DMd8oRSRUw2rS/XZRpkYKit8eYWGTgCtx40X4TY5uR7jZh6GPJtO3dcfB+BMpanLRwQbJOkKteZ/hahyX+OOmfRXn81YQ0iVDMrXx6P+qMGBv4e3yLsFsVVePYdVz5VzWA0kb/kgXvKMboONMR1o5cjZBSkk+AWpo+TT/bli/e6sK3MOErj04C6R7DcZukjggDIKSt/xB+8fxRO7C+aMtSqcPnjm8pzCkhGZTPxX8UcxUpk6w+USQhY+qts/5ZcdCUFbaY9geue673BZEf0n4uXJT/LJkwhWUMPyEcttRcl2hBKN+PPEHOAAwf43mCSqxmQzsttl5sbWHN6QpVdbgVkSQy9mKhwIWA15DNPI2iUjw7EM4gHSyBBxupLZLwtY5r/Kou4e+31/jFbtWvwIShWAKXyyT3G/p5GYrl9tt0r7S6dV3Gvxp1gF/wo+yaSCzN9P+BSqg6g77Oh/lGMUN6fNgEZi58xlLlG7hYqFq0JUXh9J22M0Co6Jl35y1CrY8Ur/WKAoYlm/s7cK6H+S9BOj7TODebZpeSsN8HhaDgMOgHVnF/WyLATMKqWrBcDApZcwzzvO0RvKEqJ6bGps7UcXHfgcmkuVeuRqhJDRI4aNY0Bd95TOna2Zo/tfvmRrQe4KpSWQ4xMb0X9Lkex0A7dKlKMJNT/wIiA/2bZzDIYev9NtTa0rw2A6ZA367aPFIqX+qu8xTVQ0fMOkJgyBfYzARFVR+23/Y/vaoDsPGTdokE4YzV1sFlxQsI3KWg5E7ezZja/aF3fU7GIlFYcfbhAvCADjlRG2TlmiM8ECC5CXiUuN+SLwSoF7RHB9BOmI28BFRutzkSvxaSW+EWTMESJXsnD6HdbztNan9GuQdIQfZvSh43lbmGgJsW4pv7VyrtwYB958RooSl8VaqPupS+6APUB+SKvR0QKIBDdVt4MAhhxzZqDzdk+qqO53eXztcUIcjbvFuuylKBA7CF/SZ5CjlcYWQO5JiR90ut8PDkdRlIKKUedTIysjhnKbdEKvEaClcrKB+F9J/khF9cuaz5a1bbtAmcCD9k4Kn4O4VnUUSK8+OllLpB/qIVWfuRJoFyVxb0b+UaSM1FanNF4KTmV6aVfl8DswYXOeS2KizDfYrRU5P7qAQRw22axxxhZMtBn4naoh35OdByjCjx8ZnueiCaMtsWahnPrfwtNPMdbVothVjoi2ZiNIfb28cdeWlaapo5ZN7gYaRxfSEZdPAhdPQPjVJMrwrQtpnvpKtnfHRxvAsDOjbxtjTXjdE0OhYmUSsYk0wNrlHC8gvBEopA1grd2xqwPfa8pKyfERNwZHWJSiCHf49wFKGsXGC/sQOMUrEH/oR7nucXXqTI2dnuxyNAL8SUu9ZlprqTBW/U30ha/HLRcmnOB4o82lclgU2CABGJiRVGKhlO3ExGhOg+xRqZxJgt4mej5rpA1335D6Lnio0PiBtyeEV6v/lQ5EVMNESEd1RS01R31zeTZeuF1VU084z5aH82BC3h9gaF/JXIys9UzlQ76un9mHtxMKT/ZFlZGroG8WLEpD/mR4mXIwtyemvfB6bYh/uFABuP53Vosg0JgjASaGOmoQ==","X-Forefront-Antispam-Report":"CIP:165.204.84.17; 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Ip=[165.204.84.17];\n Helo=[satlexmb07.amd.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n SJ1PEPF00001CDF.namprd05.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"BY5PR12MB4196","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.043,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-Mailman-Approved-At":"Thu, 19 Feb 2026 08:55:36 -0500","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Change kvm_put_apic_state() and kvm_get_apic_state() to accept a void *\ninstead of struct kvm_lapic_state *, so they can work with both the\nlegacy 1KB and the 4KB LAPIC2 register layout in later patches.\n\nUpdate kvm_apic_set_reg() and kvm_apic_get_reg() to take void * with\nexplicit char * casts for correct pointer arithmetic.\n\nThis is a preparation for LAPIC2 ioctl space and extended LVT for AMD\nchanges.\n\nNo functional change intended.\n\nSigned-off-by: Manali Shukla \n---\n hw/i386/kvm/apic.c | 48 +++++++++++++++++++-------------------\n target/i386/kvm/kvm_i386.h | 2 +-\n 2 files changed, 25 insertions(+), 25 deletions(-)","diff":"diff --git a/hw/i386/kvm/apic.c b/hw/i386/kvm/apic.c\nindex 1be9bfe36e..c1866c3939 100644\n--- a/hw/i386/kvm/apic.c\n+++ b/hw/i386/kvm/apic.c\n@@ -19,48 +19,48 @@\n #include \"kvm/kvm_i386.h\"\n #include \"kvm/tdx.h\"\n \n-static inline void kvm_apic_set_reg(struct kvm_lapic_state *kapic,\n- int reg_id, uint32_t val)\n+static inline void kvm_apic_set_reg(void *regs, int reg_id, uint32_t val)\n {\n- *((uint32_t *)(kapic->regs + (reg_id << 4))) = val;\n+ *((uint32_t *)((char *)regs + (reg_id << 4))) = val;\n }\n \n-static inline uint32_t kvm_apic_get_reg(struct kvm_lapic_state *kapic,\n- int reg_id)\n+static inline uint32_t kvm_apic_get_reg(void *regs, int reg_id)\n {\n- return *((uint32_t *)(kapic->regs + (reg_id << 4)));\n+ return *((uint32_t *)((char *)regs + (reg_id << 4)));\n }\n \n-static void kvm_put_apic_state(APICCommonState *s, struct kvm_lapic_state *kapic)\n+static void kvm_put_apic_state(APICCommonState *s, void *regs)\n {\n int i;\n \n- memset(kapic, 0, sizeof(*kapic));\n+ memset(regs, 0, KVM_APIC_REG_SIZE);\n+\n if (kvm_has_x2apic_api() && s->apicbase & MSR_IA32_APICBASE_EXTD) {\n- kvm_apic_set_reg(kapic, 0x2, s->initial_apic_id);\n+ kvm_apic_set_reg(regs, 0x2, s->initial_apic_id);\n } else {\n- kvm_apic_set_reg(kapic, 0x2, s->id << 24);\n+ kvm_apic_set_reg(regs, 0x2, s->id << 24);\n }\n- kvm_apic_set_reg(kapic, 0x8, s->tpr);\n- kvm_apic_set_reg(kapic, 0xd, s->log_dest << 24);\n- kvm_apic_set_reg(kapic, 0xe, s->dest_mode << 28 | 0x0fffffff);\n- kvm_apic_set_reg(kapic, 0xf, s->spurious_vec);\n+ kvm_apic_set_reg(regs, 0x8, s->tpr);\n+ kvm_apic_set_reg(regs, 0xd, s->log_dest << 24);\n+ kvm_apic_set_reg(regs, 0xe, s->dest_mode << 28 | 0x0fffffff);\n+ kvm_apic_set_reg(regs, 0xf, s->spurious_vec);\n for (i = 0; i < 8; i++) {\n- kvm_apic_set_reg(kapic, 0x10 + i, s->isr[i]);\n- kvm_apic_set_reg(kapic, 0x18 + i, s->tmr[i]);\n- kvm_apic_set_reg(kapic, 0x20 + i, s->irr[i]);\n+ kvm_apic_set_reg(regs, 0x10 + i, s->isr[i]);\n+ kvm_apic_set_reg(regs, 0x18 + i, s->tmr[i]);\n+ kvm_apic_set_reg(regs, 0x20 + i, s->irr[i]);\n }\n- kvm_apic_set_reg(kapic, 0x28, s->esr);\n- kvm_apic_set_reg(kapic, 0x30, s->icr[0]);\n- kvm_apic_set_reg(kapic, 0x31, s->icr[1]);\n+ kvm_apic_set_reg(regs, 0x28, s->esr);\n+ kvm_apic_set_reg(regs, 0x30, s->icr[0]);\n+ kvm_apic_set_reg(regs, 0x31, s->icr[1]);\n for (i = 0; i < APIC_LVT_NB; i++) {\n- kvm_apic_set_reg(kapic, 0x32 + i, s->lvt[i]);\n+ kvm_apic_set_reg(regs, 0x32 + i, s->lvt[i]);\n }\n- kvm_apic_set_reg(kapic, 0x38, s->initial_count);\n- kvm_apic_set_reg(kapic, 0x3e, s->divide_conf);\n+ kvm_apic_set_reg(regs, 0x38, s->initial_count);\n+ kvm_apic_set_reg(regs, 0x3e, s->divide_conf);\n+\n }\n \n-void kvm_get_apic_state(DeviceState *dev, struct kvm_lapic_state *kapic)\n+void kvm_get_apic_state(DeviceState *dev, void *kapic)\n {\n APICCommonState *s = APIC_COMMON(dev);\n int i, v;\ndiff --git a/target/i386/kvm/kvm_i386.h b/target/i386/kvm/kvm_i386.h\nindex 5f83e8850a..ecf21c2cc1 100644\n--- a/target/i386/kvm/kvm_i386.h\n+++ b/target/i386/kvm/kvm_i386.h\n@@ -56,7 +56,7 @@ bool kvm_has_adjust_clock_stable(void);\n bool kvm_has_exception_payload(void);\n void kvm_synchronize_all_tsc(void);\n \n-void kvm_get_apic_state(DeviceState *d, struct kvm_lapic_state *kapic);\n+void kvm_get_apic_state(DeviceState *d, void *kapic);\n void kvm_put_apicbase(X86CPU *cpu, uint64_t value);\n \n bool kvm_has_x2apic_api(void);\n","prefixes":["v1","1/8"]}