{"id":2198167,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2198167/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260219054207.471303-5-manali.shukla@amd.com>","date":"2026-02-19T05:42:03","name":"[v1,4/8] i386/kvm: Add extended APIC state to APICCommonState","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"684aee3d2bdf23ac98690a46e1e8054871416f14","submitter":{"id":90099,"url":"http://patchwork.ozlabs.org/api/1.0/people/90099/?format=json","name":"Manali Shukla","email":"manali.shukla@amd.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260219054207.471303-5-manali.shukla@amd.com/mbox/","series":[{"id":492683,"url":"http://patchwork.ozlabs.org/api/1.0/series/492683/?format=json","date":"2026-02-19T05:42:03","name":"i386/kvm: Add support for extended APIC register space","version":1,"mbox":"http://patchwork.ozlabs.org/series/492683/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2198167/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=amd.com header.i=@amd.com header.a=rsa-sha256\n header.s=selector1 header.b=Wqc+xf5t;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Tsirkin\"\n , \"Paolo Bonzini\" , Sean Christopherson\n , Richard Henderson , Naveen\n N Rao , Nikunj Dadhaniya ,\n ","Subject":"[PATCH v1 4/8] i386/kvm: Add extended APIC state to APICCommonState","Date":"Thu, 19 Feb 2026 05:42:03 +0000","Message-ID":"<20260219054207.471303-5-manali.shukla@amd.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260219054207.471303-1-manali.shukla@amd.com>","References":"<20260219054207.471303-1-manali.shukla@amd.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-Originating-IP":"[10.180.168.240]","X-ClientProxiedBy":"satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com\n (10.181.42.216)","X-EOPAttributedMessage":"0","X-MS-PublicTrafficType":"Email","X-MS-TrafficTypeDiagnostic":"SJ1PEPF00001CDF:EE_|SN7PR12MB7980:EE_","X-MS-Office365-Filtering-Correlation-Id":"99b1f9a2-f1db-4120-99cf-08de6f79d209","X-MS-Exchange-SenderADCheck":"1","X-MS-Exchange-AntiSpam-Relay":"0","X-Microsoft-Antispam":"BCL:0;\n ARA:13230040|36860700013|376014|7416014|1800799024|82310400026;","X-Microsoft-Antispam-Message-Info":"\n kLe+pUJi/o8VvMdbR/5+A9KDtfLV8foAEEpv3PLhsJhMh8s6f2uRoETJCu0eFuseKKo0tfGD3HFxEl1XNEwh9o46YGR+4tMsqy358PXDXf/lOk41j1JuNbmDZM1KFdeRArvdIIiVvMZJEidEhalmZApfsTAVYVt6ajBJ15fbqSZo/g5HiYhtD5YUtDmvipMeIhw3AI4nKOc/WtMkdOCwn1DEtuL/191Xs6l5H8ge3epkDWF+7sZJ5Nr3PTPuvPBTuqleMl/aI473PEZkgFCW54dICQcmyBPxBV/VFxmMakv9BK3KJvATX+cZGGDaHRQAU6mmoSrGAH3i9Ri1WQHaPWQm8moMiucQ2Ak1XdQbUOLRNeIvbzkdER7m9EmFiqTAJreh0vSbJCiH72GVeUc+V0MNlFnNGvJIceGsH6tPClEoBO/i06txuJpD+jMqgLsHoNOi+uJNQnS0j43/St8mGQ+nOjqMEoVS79yE9n8ykLN0Vfi+f90UDe4A1QjvaZUyZqYmWi8R873wYU+ghyD0CxnGkwr01DiOgrYPJQcx59PzrQCcl9GRJ67TjvS4xu3yWOqbduJyhuaP2W++TrdbfomHDe57ARApdjolkTB23v1jE+rFjhdc/BWyLGJd4lPiEydGm+Ew8ng0aA4O4FslmcYM+Jg+ShYYT+PRzyTcNF0C95M1CI+/MzHMenCD5nQ1pb3VXsQOX5Ln2yMwe42bebvAizXFCCLDBUd1+wxJEL0bZaYcsi3SQz0BYrWjvEWfrrJdu1sSZLH0iJN6viaqF8KQN7l3Gw2363wCh2fdcXlKdgz2jE/HweMAHCS97O00SIyqD2kulReN1lhWh3rH0nuCZTTx7Rz9CRn2LQGsNCDxOKg7Eft+56vCiSNdmN0rNutldDxFXcK4rVmrdYDEn72DeCj88zc+oxt/sNn7Te+8gq0MZIbWKWJ5ixCIuo0Y4b+yXvNPC8wbHEVhmBFDgSqTZpllfKdiABLZfS+85msTEagGHQ63DQlDywt4EIqv+OnEPQGD1PKsCRYFFBU+6ar2KY5s0GixnCZdaqf7OCtbPxu+FgbvfdQW0UrfO123d/ZImESc2UBXdgr6xUgX+K/w8KbhHoNrcbpS3tqCVGkk/nNmVvpRebas+ETCJiILq2S8jqu9dWPXGp9Wly59lSFqrziqy6syE/57CIonavCvJbFVmypawYNVyfwwVJUrilryHDfCbsyHiT/HQBf8LEzaXOFty7rYwD4/IQWw4r+3qOQm5o5kmzqNOoaepqyM95LjWHnXVZ3rdKdoLnPAHkP8+C8m6uWNSg2GqtCQALviFWBh9/Kyk98i2bPc/RP2NYwYH/z2Rh6uIDoPtgpQknazCEy3KLNIA7ptEKXYz8qyzPfAYgTev1FKej7M0HqU/VhuJ/42EkIJupS2SnWxyKfKH+2UBbJT66tYWbrryjBPHpZEc8e+MLlmUKhNoa4Csu8pHjVZ0JyFDbKcYv3jeNSALiA9Y9E+gqQqBECYrGFyNcdOQr72S38oqGBBoCdnwcN4jY5zEVubR9OZI4Hf25vGSAXrTdAiJzUFsqtsCbxnIr9fqdwCNe3Fvyl2S6U+4TL2+SVJSvSRK29OlT8la8T101qJhWTzmFUaKQpdTTA2FtgiHak/v5X6ahcOJMA54LvzA7BbZJ7IrKQUmEo+YQ==","X-Forefront-Antispam-Report":"CIP:165.204.84.17; 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Ip=[165.204.84.17];\n Helo=[satlexmb07.amd.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n SJ1PEPF00001CDF.namprd05.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"SN7PR12MB7980","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.043,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-Mailman-Approved-At":"Thu, 19 Feb 2026 08:55:34 -0500","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Add extended LAPIC state fields to APICCommonState to support AMD's\nextended APIC registers:\n\n- efeat: Extended Features register\n- ectrl: Extended Control register\n- extlvt: Array of extended interrupt LVT registers\n- nr_extlvt: Number of extended LVT entries\n\nThese fields store the state of AMD's extended APIC registers which\nprovide additional extended local interrupt vectors beyond the standard\nAPIC LVT entries.\n\nAdd kvm_initialize_extlvt() and kvm_uninitialize_extlvt() to manage\nthe lifecycle of extended LVT registers. Dynamically allocate and free\nthe array in APICCommonState based on nr_extlvt supported.\n\nSigned-off-by: Manali Shukla \n---\n hw/i386/kvm/apic.c | 21 +++++++++++++++++++++\n include/hw/i386/apic_internal.h | 4 ++++\n target/i386/kvm/kvm_i386.h | 2 ++\n 3 files changed, 27 insertions(+)","diff":"diff --git a/hw/i386/kvm/apic.c b/hw/i386/kvm/apic.c\nindex 9489614bca..7bec7909e9 100644\n--- a/hw/i386/kvm/apic.c\n+++ b/hw/i386/kvm/apic.c\n@@ -135,6 +135,27 @@ static void kvm_apic_vapic_base_update(APICCommonState *s)\n }\n }\n \n+void kvm_initialize_extlvt(X86CPU *cpu, uint32_t nr_extlvt)\n+{\n+ APICCommonState *s;\n+ s = APIC_COMMON(cpu->apic_state);\n+\n+ s->nr_extlvt = nr_extlvt;\n+ s->extlvt = g_malloc0(nr_extlvt * sizeof(uint32_t));\n+}\n+\n+void kvm_uninitialize_extlvt(X86CPU *cpu)\n+{\n+ APICCommonState *s;\n+ s = APIC_COMMON(cpu->apic_state);\n+\n+ if (s->extlvt) {\n+ g_free(s->extlvt);\n+ s->extlvt = NULL;\n+ s->nr_extlvt = 0;\n+ }\n+}\n+\n static void kvm_apic_put(CPUState *cs, run_on_cpu_data data)\n {\n APICCommonState *s = data.host_ptr;\ndiff --git a/include/hw/i386/apic_internal.h b/include/hw/i386/apic_internal.h\nindex 865b7ed567..e84cbed7f6 100644\n--- a/include/hw/i386/apic_internal.h\n+++ b/include/hw/i386/apic_internal.h\n@@ -174,7 +174,11 @@ struct APICCommonState {\n uint32_t lvt[APIC_LVT_NB];\n uint32_t esr; /* error register */\n uint32_t icr[2];\n+ uint32_t efeat;\n+ uint32_t ectrl;\n+ uint32_t *extlvt;\n \n+ uint32_t nr_extlvt;\n uint32_t divide_conf;\n int count_shift;\n uint32_t initial_count;\ndiff --git a/target/i386/kvm/kvm_i386.h b/target/i386/kvm/kvm_i386.h\nindex 00f8ae0ee4..338433eb52 100644\n--- a/target/i386/kvm/kvm_i386.h\n+++ b/target/i386/kvm/kvm_i386.h\n@@ -73,6 +73,8 @@ struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,\n uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg);\n uint32_t kvm_x86_build_cpuid(CPUX86State *env, struct kvm_cpuid_entry2 *entries,\n uint32_t cpuid_i);\n+void kvm_initialize_extlvt(X86CPU *cpu, uint32_t nr_extlvt);\n+void kvm_uninitialize_extlvt(X86CPU *cpu);\n #endif /* CONFIG_KVM */\n \n void kvm_pc_setup_irq_routing(bool pci_enabled);\n","prefixes":["v1","4/8"]}