{"id":2198060,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2198060/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260219090103.33697-4-skolothumtho@nvidia.com>","date":"2026-02-19T09:01:01","name":"[v7,3/5] hw/arm/smmuv3-accel: Allocate vEVENTQ for accelerated SMMUv3 devices","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"80d9ef8c8626bcc4d7f544aa26c11714821992de","submitter":{"id":91580,"url":"http://patchwork.ozlabs.org/api/1.0/people/91580/?format=json","name":"Shameer Kolothum","email":"skolothumtho@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260219090103.33697-4-skolothumtho@nvidia.com/mbox/","series":[{"id":492651,"url":"http://patchwork.ozlabs.org/api/1.0/series/492651/?format=json","date":"2026-02-19T09:01:03","name":"vEVENTQ support for accelerated SMMUv3 devices","version":7,"mbox":"http://patchwork.ozlabs.org/series/492651/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2198060/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=NKo52WTo;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n SA2PEPF00003F67.namprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"DS0PR12MB8320","X-Spam_score_int":"-10","X-Spam_score":"-1.1","X-Spam_bar":"-","X-Spam_report":"(-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.043,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Nicolin Chen \n\nWhen the guest enables the Event Queue and a vIOMMU is present, allocate a\nvEVENTQ object so that host-side events related to the vIOMMU can be\nreceived and propagated back to the guest.\n\nFor cold-plugged devices using SMMUv3 acceleration, the vIOMMU is created\nbefore the guest boots. In this case, the vEVENTQ is allocated when the\nguest writes to SMMU_CR0 and sets EVENTQEN = 1.\n\nIf no cold-plugged device exists at boot (i.e. no vIOMMU initially), the\nvEVENTQ is allocated when a vIOMMU is created, i.e. during the first\ndevice hot-plug.\n\nErrors from command queue consumption and vEVENTQ allocation are reported\nindependently as the two operations are unrelated.\n\nEvent read and propagation will be added in a later patch.\n\nSigned-off-by: Nicolin Chen \nReviewed-by: Eric Auger \nTested-by: Nicolin Chen \nSigned-off-by: Shameer Kolothum \n---\n hw/arm/smmuv3-accel.h | 6 +++++\n hw/arm/smmuv3-accel.c | 61 +++++++++++++++++++++++++++++++++++++++++--\n hw/arm/smmuv3.c | 6 +++++\n 3 files changed, 71 insertions(+), 2 deletions(-)","diff":"diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h\nindex a8a64802ec..dba6c71de5 100644\n--- a/hw/arm/smmuv3-accel.h\n+++ b/hw/arm/smmuv3-accel.h\n@@ -22,6 +22,7 @@\n */\n typedef struct SMMUv3AccelState {\n IOMMUFDViommu *viommu;\n+ IOMMUFDVeventq *veventq;\n uint32_t bypass_hwpt_id;\n uint32_t abort_hwpt_id;\n QLIST_HEAD(, SMMUv3AccelDevice) device_list;\n@@ -50,6 +51,7 @@ bool smmuv3_accel_attach_gbpa_hwpt(SMMUv3State *s, Error **errp);\n bool smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd, SMMUDevice *sdev,\n Error **errp);\n void smmuv3_accel_idr_override(SMMUv3State *s);\n+bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp);\n void smmuv3_accel_reset(SMMUv3State *s);\n #else\n static inline void smmuv3_accel_init(SMMUv3State *s)\n@@ -80,6 +82,10 @@ smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd, SMMUDevice *sdev,\n static inline void smmuv3_accel_idr_override(SMMUv3State *s)\n {\n }\n+static inline bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp)\n+{\n+ return true;\n+}\n static inline void smmuv3_accel_reset(SMMUv3State *s)\n {\n }\ndiff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c\nindex c19c526fca..f703ea1aac 100644\n--- a/hw/arm/smmuv3-accel.c\n+++ b/hw/arm/smmuv3-accel.c\n@@ -390,6 +390,19 @@ bool smmuv3_accel_issue_inv_cmd(SMMUv3State *bs, void *cmd, SMMUDevice *sdev,\n sizeof(Cmd), &entry_num, cmd, errp);\n }\n \n+static void smmuv3_accel_free_veventq(SMMUv3AccelState *accel)\n+{\n+ IOMMUFDVeventq *veventq = accel->veventq;\n+\n+ if (!veventq) {\n+ return;\n+ }\n+ close(veventq->veventq_fd);\n+ iommufd_backend_free_id(accel->viommu->iommufd, veventq->veventq_id);\n+ g_free(veventq);\n+ accel->veventq = NULL;\n+}\n+\n static void smmuv3_accel_free_viommu(SMMUv3AccelState *accel)\n {\n IOMMUFDViommu *viommu = accel->viommu;\n@@ -397,6 +410,7 @@ static void smmuv3_accel_free_viommu(SMMUv3AccelState *accel)\n if (!viommu) {\n return;\n }\n+ smmuv3_accel_free_veventq(accel);\n iommufd_backend_free_id(viommu->iommufd, accel->bypass_hwpt_id);\n iommufd_backend_free_id(viommu->iommufd, accel->abort_hwpt_id);\n iommufd_backend_free_id(viommu->iommufd, accel->viommu->viommu_id);\n@@ -404,6 +418,41 @@ static void smmuv3_accel_free_viommu(SMMUv3AccelState *accel)\n accel->viommu = NULL;\n }\n \n+bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp)\n+{\n+ SMMUv3AccelState *accel = s->s_accel;\n+ IOMMUFDVeventq *veventq;\n+ uint32_t veventq_id;\n+ uint32_t veventq_fd;\n+\n+ if (!accel || !accel->viommu) {\n+ return true;\n+ }\n+\n+ if (accel->veventq) {\n+ return true;\n+ }\n+\n+ if (!smmuv3_eventq_enabled(s)) {\n+ return true;\n+ }\n+\n+ if (!iommufd_backend_alloc_veventq(accel->viommu->iommufd,\n+ accel->viommu->viommu_id,\n+ IOMMU_VEVENTQ_TYPE_ARM_SMMUV3,\n+ 1 << s->eventq.log2size, &veventq_id,\n+ &veventq_fd, errp)) {\n+ return false;\n+ }\n+\n+ veventq = g_new0(IOMMUFDVeventq, 1);\n+ veventq->veventq_id = veventq_id;\n+ veventq->veventq_fd = veventq_fd;\n+ veventq->viommu = accel->viommu;\n+ accel->veventq = veventq;\n+ return true;\n+}\n+\n static bool\n smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n Error **errp)\n@@ -429,6 +478,7 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n viommu->viommu_id = viommu_id;\n viommu->s2_hwpt_id = s2_hwpt_id;\n viommu->iommufd = idev->iommufd;\n+ accel->viommu = viommu;\n \n /*\n * Pre-allocate HWPTs for S1 bypass and abort cases. These will be attached\n@@ -448,14 +498,20 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n goto free_abort_hwpt;\n }\n \n+ /* Allocate a vEVENTQ if guest has enabled event queue */\n+ if (!smmuv3_accel_alloc_veventq(s, errp)) {\n+ goto free_bypass_hwpt;\n+ }\n+\n /* Attach a HWPT based on SMMUv3 GBPA.ABORT value */\n hwpt_id = smmuv3_accel_gbpa_hwpt(s, accel);\n if (!host_iommu_device_iommufd_attach_hwpt(idev, hwpt_id, errp)) {\n- goto free_bypass_hwpt;\n+ goto free_veventq;\n }\n- accel->viommu = viommu;\n return true;\n \n+free_veventq:\n+ smmuv3_accel_free_veventq(accel);\n free_bypass_hwpt:\n iommufd_backend_free_id(idev->iommufd, accel->bypass_hwpt_id);\n free_abort_hwpt:\n@@ -463,6 +519,7 @@ free_abort_hwpt:\n free_viommu:\n iommufd_backend_free_id(idev->iommufd, viommu->viommu_id);\n g_free(viommu);\n+ accel->viommu = NULL;\n return false;\n }\n \ndiff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c\nindex c08d58c579..5d718da764 100644\n--- a/hw/arm/smmuv3.c\n+++ b/hw/arm/smmuv3.c\n@@ -1605,6 +1605,12 @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset,\n s->cr0ack = data & ~SMMU_CR0_RESERVED;\n /* in case the command queue has been enabled */\n smmuv3_cmdq_consume(s, &local_err);\n+ if (local_err) {\n+ error_report_err(local_err);\n+ local_err = NULL;\n+ }\n+ /* Allocate vEVENTQ if EVENTQ is enabled and a vIOMMU is available */\n+ smmuv3_accel_alloc_veventq(s, &local_err);\n break;\n case A_CR1:\n s->cr[1] = data;\n","prefixes":["v7","3/5"]}