{"id":2198059,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2198059/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260219090103.33697-3-skolothumtho@nvidia.com>","date":"2026-02-19T09:01:00","name":"[v7,2/5] hw/arm/smmuv3-accel: Add viommu free helper","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"be79f1a07246bf47d1a9fe3e5ba8eacdff09639d","submitter":{"id":91580,"url":"http://patchwork.ozlabs.org/api/1.0/people/91580/?format=json","name":"Shameer Kolothum","email":"skolothumtho@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260219090103.33697-3-skolothumtho@nvidia.com/mbox/","series":[{"id":492651,"url":"http://patchwork.ozlabs.org/api/1.0/series/492651/?format=json","date":"2026-02-19T09:01:03","name":"vEVENTQ support for accelerated SMMUv3 devices","version":7,"mbox":"http://patchwork.ozlabs.org/series/492651/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2198059/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=bJWQuLNQ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n SA2PEPF00003F66.namprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"LV3PR12MB9216","X-Spam_score_int":"-10","X-Spam_score":"-1.1","X-Spam_bar":"-","X-Spam_report":"(-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.043,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Move viommu teardown into a helper function and use it from the\nlast device removal path. No functional change.\n\nReviewed-by: Nicolin Chen \nReviewed-by: Eric Auger \nTested-by: Nicolin Chen \nSigned-off-by: Shameer Kolothum \n---\n hw/arm/smmuv3-accel.c | 21 +++++++++++++++------\n 1 file changed, 15 insertions(+), 6 deletions(-)","diff":"diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c\nindex f5cd4df336..c19c526fca 100644\n--- a/hw/arm/smmuv3-accel.c\n+++ b/hw/arm/smmuv3-accel.c\n@@ -390,6 +390,20 @@ bool smmuv3_accel_issue_inv_cmd(SMMUv3State *bs, void *cmd, SMMUDevice *sdev,\n sizeof(Cmd), &entry_num, cmd, errp);\n }\n \n+static void smmuv3_accel_free_viommu(SMMUv3AccelState *accel)\n+{\n+ IOMMUFDViommu *viommu = accel->viommu;\n+\n+ if (!viommu) {\n+ return;\n+ }\n+ iommufd_backend_free_id(viommu->iommufd, accel->bypass_hwpt_id);\n+ iommufd_backend_free_id(viommu->iommufd, accel->abort_hwpt_id);\n+ iommufd_backend_free_id(viommu->iommufd, accel->viommu->viommu_id);\n+ g_free(viommu);\n+ accel->viommu = NULL;\n+}\n+\n static bool\n smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n Error **errp)\n@@ -549,12 +563,7 @@ static void smmuv3_accel_unset_iommu_device(PCIBus *bus, void *opaque,\n trace_smmuv3_accel_unset_iommu_device(devfn, idev->devid);\n \n if (QLIST_EMPTY(&accel->device_list)) {\n- iommufd_backend_free_id(accel->viommu->iommufd, accel->bypass_hwpt_id);\n- iommufd_backend_free_id(accel->viommu->iommufd, accel->abort_hwpt_id);\n- iommufd_backend_free_id(accel->viommu->iommufd,\n- accel->viommu->viommu_id);\n- g_free(accel->viommu);\n- accel->viommu = NULL;\n+ smmuv3_accel_free_viommu(accel);\n }\n }\n \n","prefixes":["v7","2/5"]}