{"id":2198058,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2198058/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260219090103.33697-5-skolothumtho@nvidia.com>","date":"2026-02-19T09:01:02","name":"[v7,4/5] hw/arm/smmuv3: Introduce a helper function for event propagation","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"f9713ccc1088b8076758b2c75c5007622d2e252d","submitter":{"id":91580,"url":"http://patchwork.ozlabs.org/api/1.0/people/91580/?format=json","name":"Shameer Kolothum","email":"skolothumtho@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260219090103.33697-5-skolothumtho@nvidia.com/mbox/","series":[{"id":492651,"url":"http://patchwork.ozlabs.org/api/1.0/series/492651/?format=json","date":"2026-02-19T09:01:03","name":"vEVENTQ support for accelerated SMMUv3 devices","version":7,"mbox":"http://patchwork.ozlabs.org/series/492651/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2198058/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=FDb8N6vO;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n SJ5PEPF000001D6.namprd05.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"SJ0PR12MB5663","X-Spam_score_int":"-10","X-Spam_score":"-1.1","X-Spam_bar":"-","X-Spam_report":"(-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.043,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Factor out the code that propagates event records to the guest into a\nhelper function. The accelerated SMMUv3 path can use this to propagate\nhost events in a subsequent patch.\n\nTake the mutex inside the helper before accessing the Event Queue.\nToday event propagation occurs only in the core SMMUv3 path and is\neffectively serialized. A subsequent patch will also invoke this helper\nfrom the accelerated event read path, which may run concurrently.\nTherefore serialization is required here.\n\nNo functional change intended.\n\nReviewed-by: Nicolin Chen \nReviewed-by: Eric Auger \nTested-by: Nicolin Chen \nSigned-off-by: Shameer Kolothum \n---\n hw/arm/smmuv3-internal.h | 4 ++++\n hw/arm/smmuv3.c | 20 ++++++++++++++------\n hw/arm/trace-events | 2 +-\n 3 files changed, 19 insertions(+), 7 deletions(-)","diff":"diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h\nindex a6464425ec..b666109ad9 100644\n--- a/hw/arm/smmuv3-internal.h\n+++ b/hw/arm/smmuv3-internal.h\n@@ -352,7 +352,11 @@ typedef struct SMMUEventInfo {\n (x)->word[6] = (uint32_t)(addr & 0xffffffff); \\\n } while (0)\n \n+#define EVT_GET_TYPE(x) extract32((x)->word[0], 0, 8)\n+#define EVT_GET_SID(x) ((x)->word[1])\n+\n void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *event);\n+void smmuv3_propagate_event(SMMUv3State *s, Evt *evt);\n int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, SMMUEventInfo *event);\n \n static inline int oas2bits(int oas_field)\ndiff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c\nindex 5d718da764..af7a54143f 100644\n--- a/hw/arm/smmuv3.c\n+++ b/hw/arm/smmuv3.c\n@@ -168,10 +168,22 @@ static MemTxResult smmuv3_write_eventq(SMMUv3State *s, Evt *evt)\n return MEMTX_OK;\n }\n \n+void smmuv3_propagate_event(SMMUv3State *s, Evt *evt)\n+{\n+ MemTxResult r;\n+\n+ trace_smmuv3_propagate_event(smmu_event_string(EVT_GET_TYPE(evt)),\n+ EVT_GET_SID(evt));\n+ QEMU_LOCK_GUARD(&s->mutex);\n+ r = smmuv3_write_eventq(s, evt);\n+ if (r != MEMTX_OK) {\n+ smmuv3_trigger_irq(s, SMMU_IRQ_GERROR, R_GERROR_EVENTQ_ABT_ERR_MASK);\n+ }\n+}\n+\n void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *info)\n {\n Evt evt = {};\n- MemTxResult r;\n \n if (!smmuv3_eventq_enabled(s)) {\n return;\n@@ -251,11 +263,7 @@ void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *info)\n g_assert_not_reached();\n }\n \n- trace_smmuv3_record_event(smmu_event_string(info->type), info->sid);\n- r = smmuv3_write_eventq(s, &evt);\n- if (r != MEMTX_OK) {\n- smmuv3_trigger_irq(s, SMMU_IRQ_GERROR, R_GERROR_EVENTQ_ABT_ERR_MASK);\n- }\n+ smmuv3_propagate_event(s, &evt);\n info->recorded = true;\n }\n \ndiff --git a/hw/arm/trace-events b/hw/arm/trace-events\nindex 8135c0c734..3457536fb0 100644\n--- a/hw/arm/trace-events\n+++ b/hw/arm/trace-events\n@@ -40,7 +40,7 @@ smmuv3_cmdq_opcode(const char *opcode) \"<--- %s\"\n smmuv3_cmdq_consume_out(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) \"prod:%d, cons:%d, prod_wrap:%d, cons_wrap:%d \"\n smmuv3_cmdq_consume_error(const char *cmd_name, uint8_t cmd_error) \"Error on %s command execution: %d\"\n smmuv3_write_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) \"addr: 0x%\"PRIx64\" val:0x%\"PRIx64\" size: 0x%x(%d)\"\n-smmuv3_record_event(const char *type, uint32_t sid) \"%s sid=0x%x\"\n+smmuv3_propagate_event(const char *type, uint32_t sid) \"%s sid=0x%x\"\n smmuv3_find_ste(uint16_t sid, uint32_t features, uint16_t sid_split) \"sid=0x%x features:0x%x, sid_split:0x%x\"\n smmuv3_find_ste_2lvl(uint64_t strtab_base, uint64_t l1ptr, int l1_ste_offset, uint64_t l2ptr, int l2_ste_offset, int max_l2_ste) \"strtab_base:0x%\"PRIx64\" l1ptr:0x%\"PRIx64\" l1_off:0x%x, l2ptr:0x%\"PRIx64\" l2_off:0x%x max_l2_ste:%d\"\n smmuv3_get_ste(uint64_t addr) \"STE addr: 0x%\"PRIx64\n","prefixes":["v7","4/5"]}