{"id":2198050,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2198050/?format=json","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.0/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260219081318.4156901-3-den@valinux.co.jp>","date":"2026-02-19T08:13:13","name":"[v9,2/7] PCI: dwc: Record integrated eDMA register window","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"981bb241d0180d4809748f98c919e4076d16bb26","submitter":{"id":91573,"url":"http://patchwork.ozlabs.org/api/1.0/people/91573/?format=json","name":"Koichiro Den","email":"den@valinux.co.jp"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260219081318.4156901-3-den@valinux.co.jp/mbox/","series":[{"id":492647,"url":"http://patchwork.ozlabs.org/api/1.0/series/492647/?format=json","date":"2026-02-19T08:13:11","name":"PCI: endpoint: pci-ep-msi: Add embedded doorbell fallback","version":9,"mbox":"http://patchwork.ozlabs.org/series/492647/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2198050/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=valinux.co.jp header.i=@valinux.co.jp\n header.a=rsa-sha256 header.s=selector1 header.b=SI1NLZsA;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n 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bh=IpMBWHmKo9m4Bn5DsWqxUnKAG8hRFfAVV32vx7GzjJU=;\n b=SI1NLZsAyqs/we7tespx1cs5m0rt6KO29Bm9Is+SO6DaOK0zBCOOeUQrbwAdyqvwEPB0EjUkkZkaB5Y5XL5hRbV99SEGegUASsfrW9ky54knt8n1n5C4/gaMgMRzG9uDj/hFo1SnfprL5mQWpQZK87sGZ0DajPhkqhPLTlY5xjE=","From":"Koichiro Den ","To":"jingoohan1@gmail.com,\n\tmani@kernel.org,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\trobh@kernel.org,\n\tbhelgaas@google.com,\n\tkishon@kernel.org,\n\tjdmason@kudzu.us,\n\tdave.jiang@intel.com,\n\tallenbh@gmail.com,\n\tcassel@kernel.org,\n\tFrank.Li@nxp.com,\n\tshinichiro.kawasaki@wdc.com,\n\tchristian.bruel@foss.st.com","Cc":"mmaddireddy@nvidia.com,\n\tlinux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tntb@lists.linux.dev","Subject":"[PATCH v9 2/7] PCI: dwc: Record integrated eDMA register window","Date":"Thu, 19 Feb 2026 17:13:13 +0900","Message-ID":"<20260219081318.4156901-3-den@valinux.co.jp>","X-Mailer":"git-send-email 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V1+NxHrQKt6HF+MpUCEs8LbXx4tmOUzFoVVC3WS/aZscgcU469v9uoYIfRUUxV7Cw+CTvojIbAj39nNnhyffvVHfIBHtJnzUpb/XbwBTi7t1gujSy+QW7UhBpdX74dWGgxSGipq5ns5YbrW8tlJ1vAiyZc5W7Czduv4I0w48gaNV6anElT//fFD0K6M42wKRVG1t2nKDcQEP68DAZp7mPjSg8rLa9/+zPTyFl99KV+uZcxWl2yjhZzuJk6h/yG/4krPk81P5CiZ42s1Qs8twlFHTKgh7EMmO9rimxi2YjKr5GC3TLNYSWr1X6iCgJZxDbtC1w7JmvPI1zpgZNFxNklsdUqhWW01fx4E/UBcxMV9PlNJaoz7HOZ2BxbguU0jk2EFdkaTcMpUqnNGYMl3zITI1nvCh0ds8gkfIH8ZuARpx3KPjBD3U0KWpRL7wu2DUlumKX7hvOO234zpLY4vcDN77zeYN2TPKt1P/AeAOZ8gfHD1umj8B+oO/bQTby4Sc+slF/jLf62stJhHFO11EKdRTShX0pfCiBQYQxDsptMecrjRspjKgmjuTHnxquRaklQ9Eyc730Cw4++PVOMugWhiNJtJjsBS/IcdMr2TVFCR4KMPL+SLxMdedIiaS2cilwn1Wtnr6WSzZIBWD8CpH89cHqmeZKxtC35BBP/gPDaGts42hyBBHJLiD8myQEjApYIkb9wzN1nFOhZq3fAz/ABcKTuKhgxRKI1fwIe04veZcMI/vKoqt4JHxy7wcLyfuQTli8DsKL+5/BhaUJdIwXo42R25o6etmcPJeWeh2bM7JTyxu3f86/BwwVDeNAhuIEfjeK4EGbOwEGDeY3XiT5e75n1e6/4SUJS2lDDDLaG0yhfEdAepUtRBBRexVeevm8fMbOatsgxjiwVpwdHlJQ8n20avvnKHrWIJS6xOFLcUwzNrALzHEhyZiHzC1nnAexnf5SipxGIaxqntnzDVG6sq93M7mlSNWYD1gR4EBaNgYEHWS2dt9hKlmgXFyZXMl7nQ2rR50E1OHjIrB+IeEgYFk4PDlwCa7tyH8GJ+Qna2b4uVvfjhhRo140N5kVfndRiD+491Wt4l6LPFm7juQvgOc2pXLBK4EFwxqZUMcrLaarjPfgWKdMc8Yta8XTsSMmgTdrgAceGEjIHFRFSG2Fj95uvrs7VZV3vdHFA/TryQQyO4k9FK1fBRVtVfJfcqgTpjinybC6im+9Imu84NqdLpWsEzopPVfQw9wAGwmPZVL2OXI+Jk7t7zrHnT7w1ZdHtfZlrf0PJvwoV8Z8nB7wMmv6pa6c63jGder/gwNL4bLCj1L+FeTnYj2e2qIDH6n53l8mKJak8zR1mW+BQ0xCSWojDobK22ALXEsceDp2GAOrxZVXm7jSlVpJxXvKAXdQcm7Wm56N0mrjwJ5CmOqCM6rJVf7DTcdsRhPm+r1O9WRt5Mzow7POduUav5SKP6i0bYuGNI8apK8VaqTXDRjQml/5CjH7RFf9zVIEpCYJBy1axpolG2M3swFMI4TPJxcZYNW5TiNXg8YoRfF12AOv1LRuvbGM/vXKpD4a9Xy/kJoJxTmHPuRW4HcoThRbcNIFWcGtqfYlf3St0PuiuidZ8FOVqvYNoKjFSeilDBfyKGwOhZQ1KHke3M/Is4V72i3KNC6ZkFYEz1qBs8n2ne8E/9i8Hb4lGvxkrlbMxWyReoqos38kSeAvCfzNK16ULrDtoHcAFT4GlByg9pTVmfDwZ1fsL+SlUWIlpKqLf5fNtH4E4OZ4TNBzlrdqvZJNCfN","X-OriginatorOrg":"valinux.co.jp","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 9c3a65ab-8b2c-44e6-9fb4-08de6f8ebffb","X-MS-Exchange-CrossTenant-AuthSource":"TY7P286MB7722.JPNP286.PROD.OUTLOOK.COM","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"19 Feb 2026 08:13:23.0825\n (UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"7a57bee8-f73d-4c5f-a4f7-d72c91c8c111","X-MS-Exchange-CrossTenant-MailboxType":"HOSTED","X-MS-Exchange-CrossTenant-UserPrincipalName":"\n aCp7sRSQKsjsz/veocWWSmFSkDz6Ivo6w9jQ7/9DUZ4vzPD/so2XhgqEc746/7bNQ1tWjovhjgwx1jeHSHqlSQ==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"TYRP286MB5862"},"content":"Some DesignWare PCIe controllers integrate an eDMA block whose registers\nare located in a dedicated register window. Endpoint function drivers\nmay need the physical base and size of this window to map/expose it to a\npeer.\n\nRecord the physical base and size of the integrated eDMA register window\nin struct dw_pcie.\n\nReviewed-by: Frank Li \nSigned-off-by: Koichiro Den \n---\n drivers/pci/controller/dwc/pcie-designware.c | 4 ++++\n drivers/pci/controller/dwc/pcie-designware.h | 2 ++\n 2 files changed, 6 insertions(+)","diff":"diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c\nindex 5741c09dde7f..f82ed189f6ae 100644\n--- a/drivers/pci/controller/dwc/pcie-designware.c\n+++ b/drivers/pci/controller/dwc/pcie-designware.c\n@@ -162,8 +162,12 @@ int dw_pcie_get_resources(struct dw_pcie *pci)\n \t\t\tpci->edma.reg_base = devm_ioremap_resource(pci->dev, res);\n \t\t\tif (IS_ERR(pci->edma.reg_base))\n \t\t\t\treturn PTR_ERR(pci->edma.reg_base);\n+\t\t\tpci->edma_reg_phys = res->start;\n+\t\t\tpci->edma_reg_size = resource_size(res);\n \t\t} else if (pci->atu_size >= 2 * DEFAULT_DBI_DMA_OFFSET) {\n \t\t\tpci->edma.reg_base = pci->atu_base + DEFAULT_DBI_DMA_OFFSET;\n+\t\t\tpci->edma_reg_phys = pci->atu_phys_addr + DEFAULT_DBI_DMA_OFFSET;\n+\t\t\tpci->edma_reg_size = pci->atu_size - DEFAULT_DBI_DMA_OFFSET;\n \t\t}\n \t}\n \ndiff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h\nindex ae6389dd9caa..52f26663e8b1 100644\n--- a/drivers/pci/controller/dwc/pcie-designware.h\n+++ b/drivers/pci/controller/dwc/pcie-designware.h\n@@ -541,6 +541,8 @@ struct dw_pcie {\n \tint\t\t\tmax_link_speed;\n \tu8\t\t\tn_fts[2];\n \tstruct dw_edma_chip\tedma;\n+\tphys_addr_t\t\tedma_reg_phys;\n+\tresource_size_t\t\tedma_reg_size;\n \tbool\t\t\tl1ss_support;\t/* L1 PM Substates support */\n \tstruct clk_bulk_data\tapp_clks[DW_PCIE_NUM_APP_CLKS];\n \tstruct clk_bulk_data\tcore_clks[DW_PCIE_NUM_CORE_CLKS];\n","prefixes":["v9","2/7"]}