{"id":2198047,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2198047/?format=json","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.0/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260219081318.4156901-4-den@valinux.co.jp>","date":"2026-02-19T08:13:14","name":"[v9,3/7] PCI: dwc: ep: Expose integrated eDMA resources via EPC aux-resource API","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"1df2e352c203fc78432343013686b5536ae10098","submitter":{"id":91573,"url":"http://patchwork.ozlabs.org/api/1.0/people/91573/?format=json","name":"Koichiro Den","email":"den@valinux.co.jp"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260219081318.4156901-4-den@valinux.co.jp/mbox/","series":[{"id":492647,"url":"http://patchwork.ozlabs.org/api/1.0/series/492647/?format=json","date":"2026-02-19T08:13:11","name":"PCI: endpoint: pci-ep-msi: Add embedded doorbell fallback","version":9,"mbox":"http://patchwork.ozlabs.org/series/492647/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2198047/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=valinux.co.jp header.i=@valinux.co.jp\n header.a=rsa-sha256 header.s=selector1 header.b=qlE7o7G2;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n 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bh=hU9Om7ps5PYQ6tQtBQfQF23SidFjmj9NTXGez67BRDc=;\n b=qlE7o7G2x0qZRfp3gxrtkP2/Agk6OCU7gLkdvfxY9D2LZmW/kxnq0vXKUz3bhky6QTLL2kbSPXt1HXREgKGfOVCyXM5JrGdvEPb2cCvxhR4uQPFDqKaRQeGtcs+VCm/wT5rXuFobsaCRbiGuvW+d1rXkHEC5qjXG2PA8VWSzuxk=","From":"Koichiro Den ","To":"jingoohan1@gmail.com,\n\tmani@kernel.org,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\trobh@kernel.org,\n\tbhelgaas@google.com,\n\tkishon@kernel.org,\n\tjdmason@kudzu.us,\n\tdave.jiang@intel.com,\n\tallenbh@gmail.com,\n\tcassel@kernel.org,\n\tFrank.Li@nxp.com,\n\tshinichiro.kawasaki@wdc.com,\n\tchristian.bruel@foss.st.com","Cc":"mmaddireddy@nvidia.com,\n\tlinux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tntb@lists.linux.dev","Subject":"[PATCH v9 3/7] PCI: dwc: ep: Expose integrated eDMA resources via EPC\n aux-resource API","Date":"Thu, 19 Feb 2026 17:13:14 +0900","Message-ID":"<20260219081318.4156901-4-den@valinux.co.jp>","X-Mailer":"git-send-email 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8i1YTrGWT8Lzc+4kCVvVSK+r0drVpDvuH0wyk8E/gH4A525LEAz9yZvb6qq/b9VKKsiTr0+kZ9Ig90etHJlJJMT+4EVvre+7o0tRO02yZcbJcI8blTp2qtLkCCUBkaLh7Cs8Du6/CmMApR3vCV2ZlujLRpy3qMTy7R+3OflhpkxHUCYCdseHpyG7uA/oAetNmFv3J6YQGiDtgogMyNGRVUY/TBdJQZpfaPxnJ22WyqLBspPitPJu5ZvDEAKZgIzv6U6gaYL0BOGdqQ9nu/dpnB47Y2jUSCjSVkVm0tg9ad/Sog9Ta0KbfzZ2CaDHLTnhNGKtu6FRReMyOrtVUBe61HnTaugJMaATvBozvs7ElGM9e1AU6RbM1oPzRTnkPI8U5KC8XJW57Uv/W/t5ShAiaGPz4Wd/etRY8xBcAxfdquR1YKAaDkMfgKu7OX0tUkxyt277wZ3X/+TVJjaANdAN/QavjhQ8Drm6TYqDqzstRCFn7QeTDlMeFZEM10YsCGJWwJL6PhT2X7Up52lMWVrcfqFi2LnXoWDk8u2NUFHCtiLaBpAQM1fXO4fW3d+UfOtOvBkFPUcVYdSg8EjCI9bmNL8n80ycateqmKm4XFpFjBfxhkFj1KGhxZXvSsGHKiKbXJKLNg5UxYnzp4dAgyqWZPOLJegwHoIFLQ/rdOf/k6RPVACRhKmkE0qWdJsJgoToQaf9AjPm9+Ho/CQqD3Wlt0dcT6mcpYl2sElh//FKb69ZJLQxnAvF/2/DK5K5nPw653YqV7deI2KYAhoKTYkxR513xi6iNs9VWHRLVN3IQUAr88cRg68+4q3esD24c3o1kLv7/LwtoiIDNGMO4KMM4vANPRCt+MR2RWMpWUVa1/pSreCQ3fCJYCD1Qy/D60n0DCrc2RAemwQkoSDB6kDQM9efKyXoD2FfYsXjd47wdxHUucLLOUAPCemDTUJb+zH9Twq3WQU5ZtczLvnrCM4xL/CI5mc/yOe94SGlbTLZRM/qxk8oDwErkSceYQmYdfnmoZLdlL+dOwkmUObYuS1AM7jWuIkQQHYR9ZcSce7jFxg9a6TaxFLYP7sGB+AEDGG4JI/Qo71WJdtChe5AJh7qzTScMnHs/AF79/tJVW6dS2s/zSCxwHcFn0GtVbunsy6xlIPyFlytYk2genD//1s3v24gZItMcTynfDj4SMpfMeAXCGF5TiBYppyGKkqidiDcWNfl9NFmW3ZRRhxT1QTysK2AKx9c5bTJY3698toFEki0CPWf8doFDW5gCDujQHMMEO5X9fy1VRDZd1Nid75+9aKHDGX+uTKn1pMwgabipHn4+nvu8Bv0eQ+PKqehkvc40YJhsE2QecKYNJ+AjKchmCspOpx04fUVSvxyRwzudKdSYwM714DCMN0C/FwswzYIC94mSes2L3+D4ZX95abyICD6xcNM62nJld3LzGMS6Z05BvJAIY4Ka71k2HyeXRKSk9ifi0sLjUQrWmwtzGjvjklzSm8aL5DH8yRnizfAHZ2ZbyvLFVdesB4OkWv0bW+TOhKRCVgSORsB5K7SC3vfeCvPInhWKadTlp/f9DhKc++byUfX+Mf950SZhtIXIdK0RWd5i1IY5WcuM02Zh0OwejK7ZsHAE52148tg6mrfI0UFxw0LfeETyC3rSbe26UElCeCiln5FS7qbBa5p1blpvq/XpSkXQ4zbYziNUsna1yYnjwa4hwHqXCAyU+YI+2HX3XodMinYA8UsbZ0kOb6ARq6t/KakutAA6Ka8rXJf9RC8hd3q1rmonLSrKhElUFPq","X-OriginatorOrg":"valinux.co.jp","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 9b4c53e0-a803-49ec-cbaa-08de6f8ec072","X-MS-Exchange-CrossTenant-AuthSource":"TY7P286MB7722.JPNP286.PROD.OUTLOOK.COM","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"19 Feb 2026 08:13:23.8648\n (UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"7a57bee8-f73d-4c5f-a4f7-d72c91c8c111","X-MS-Exchange-CrossTenant-MailboxType":"HOSTED","X-MS-Exchange-CrossTenant-UserPrincipalName":"\n Tq4QcnpTEdfw9m75BGvZpdQ9LbyKWLnMMA+rx7f3Ch5uas1vZpafIvQinjm2qyjH62wY4XX9QleuaKR8zel5WQ==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"TYRP286MB5862"},"content":"Implement the EPC aux-resource API for DesignWare endpoint controllers\nwith integrated eDMA.\n\nReport:\n - DMA controller MMIO window (PCI_EPC_AUX_DMA_CTRL_MMIO)\n - interrupt-emulation doorbell register (PCI_EPC_AUX_DOORBELL_MMIO),\n including its Linux IRQ and the data value to write to trigger the\n interrupt\n - per-channel LL descriptor regions (PCI_EPC_AUX_DMA_CHAN_DESC)\n\nIf the DMA controller MMIO window is already exposed via a\nplatform-owned fixed BAR subregion, also provide the BAR number and\noffset so EPF drivers can reuse it without reprogramming the BAR.\n\nSigned-off-by: Koichiro Den \n---\n .../pci/controller/dwc/pcie-designware-ep.c | 151 ++++++++++++++++++\n 1 file changed, 151 insertions(+)","diff":"diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c\nindex 5e47517c757c..2408ce95c103 100644\n--- a/drivers/pci/controller/dwc/pcie-designware-ep.c\n+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c\n@@ -9,6 +9,7 @@\n #include \n #include \n #include \n+#include \n #include \n \n #include \"pcie-designware.h\"\n@@ -808,6 +809,155 @@ dw_pcie_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no)\n \treturn ep->ops->get_features(ep);\n }\n \n+static const struct pci_epc_bar_rsvd_region *\n+dw_pcie_ep_find_bar_rsvd_region(struct dw_pcie_ep *ep,\n+\t\t\t\tenum pci_epc_bar_rsvd_region_type type,\n+\t\t\t\tenum pci_barno *bar,\n+\t\t\t\tresource_size_t *bar_offset)\n+{\n+\tconst struct pci_epc_features *features;\n+\tconst struct pci_epc_bar_desc *bar_desc;\n+\tconst struct pci_epc_bar_rsvd_region *r;\n+\tint i, j;\n+\n+\tif (!ep->ops->get_features)\n+\t\treturn NULL;\n+\n+\tfeatures = ep->ops->get_features(ep);\n+\tif (!features)\n+\t\treturn NULL;\n+\n+\tfor (i = BAR_0; i <= BAR_5; i++) {\n+\t\tbar_desc = &features->bar[i];\n+\n+\t\tif (!bar_desc->nr_rsvd_regions || !bar_desc->rsvd_regions)\n+\t\t\tcontinue;\n+\n+\t\tfor (j = 0; j < bar_desc->nr_rsvd_regions; j++) {\n+\t\t\tr = &bar_desc->rsvd_regions[j];\n+\n+\t\t\tif (r->type != type)\n+\t\t\t\tcontinue;\n+\n+\t\t\tif (bar)\n+\t\t\t\t*bar = i;\n+\t\t\tif (bar_offset)\n+\t\t\t\t*bar_offset = r->offset;\n+\t\t\treturn r;\n+\t\t}\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+static int\n+dw_pcie_ep_get_aux_resources(struct pci_epc *epc, u8 func_no, u8 vfunc_no,\n+\t\t\t struct pci_epc_aux_resource *resources,\n+\t\t\t int num_resources)\n+{\n+\tstruct dw_pcie_ep *ep = epc_get_drvdata(epc);\n+\tstruct dw_pcie *pci = to_dw_pcie_from_ep(ep);\n+\tconst struct pci_epc_bar_rsvd_region *rsvd;\n+\tstruct dw_edma_chip *edma = &pci->edma;\n+\tenum pci_barno dma_ctrl_bar = NO_BAR;\n+\tint ll_cnt = 0, needed, idx = 0;\n+\tresource_size_t db_offset = edma->db_offset;\n+\tresource_size_t dma_ctrl_bar_offset = 0;\n+\tresource_size_t dma_reg_size;\n+\tunsigned int i;\n+\n+\tif (!pci->edma_reg_size)\n+\t\treturn 0;\n+\n+\tdma_reg_size = pci->edma_reg_size;\n+\n+\tfor (i = 0; i < edma->ll_wr_cnt; i++)\n+\t\tif (edma->ll_region_wr[i].sz)\n+\t\t\tll_cnt++;\n+\n+\tfor (i = 0; i < edma->ll_rd_cnt; i++)\n+\t\tif (edma->ll_region_rd[i].sz)\n+\t\t\tll_cnt++;\n+\n+\tneeded = 1 + ll_cnt + (db_offset != ~0 ? 1 : 0);\n+\n+\t/* Count query mode */\n+\tif (!resources || !num_resources)\n+\t\treturn needed;\n+\n+\tif (num_resources < needed)\n+\t\treturn -ENOSPC;\n+\n+\trsvd = dw_pcie_ep_find_bar_rsvd_region(ep,\n+\t\t\t\t\t PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO,\n+\t\t\t\t\t &dma_ctrl_bar,\n+\t\t\t\t\t &dma_ctrl_bar_offset);\n+\tif (rsvd && rsvd->size < dma_reg_size)\n+\t\tdma_reg_size = rsvd->size;\n+\n+\t/* DMA register block */\n+\tresources[idx++] = (struct pci_epc_aux_resource) {\n+\t\t.type = PCI_EPC_AUX_DMA_CTRL_MMIO,\n+\t\t.phys_addr = pci->edma_reg_phys,\n+\t\t.size = dma_reg_size,\n+\t\t.bar = dma_ctrl_bar,\n+\t\t.bar_offset = dma_ctrl_bar_offset,\n+\t};\n+\n+\t/*\n+\t * For interrupt-emulation doorbells, report a standalone resource\n+\t * instead of bundling it into the DMA controller MMIO resource.\n+\t */\n+\tif (db_offset != ~0) {\n+\t\tif (range_end_overflows_t(resource_size_t, db_offset,\n+\t\t\t\t\t sizeof(u32), dma_reg_size))\n+\t\t\treturn -EINVAL;\n+\n+\t\tresources[idx++] = (struct pci_epc_aux_resource) {\n+\t\t\t.type = PCI_EPC_AUX_DOORBELL_MMIO,\n+\t\t\t.phys_addr = pci->edma_reg_phys + db_offset,\n+\t\t\t.size = sizeof(u32),\n+\t\t\t.bar = dma_ctrl_bar,\n+\t\t\t.bar_offset = dma_ctrl_bar != NO_BAR ?\n+\t\t\t\t\tdma_ctrl_bar_offset + db_offset : 0,\n+\t\t\t.u.db_mmio = {\n+\t\t\t\t.irq = edma->db_irq,\n+\t\t\t\t.data = 0, /* write 0 to assert */\n+\t\t\t},\n+\t\t};\n+\t}\n+\n+\t/* One LL region per write channel */\n+\tfor (i = 0; i < edma->ll_wr_cnt; i++) {\n+\t\tif (!edma->ll_region_wr[i].sz)\n+\t\t\tcontinue;\n+\n+\t\tresources[idx++] = (struct pci_epc_aux_resource) {\n+\t\t\t.type = PCI_EPC_AUX_DMA_CHAN_DESC,\n+\t\t\t.phys_addr = edma->ll_region_wr[i].paddr,\n+\t\t\t.size = edma->ll_region_wr[i].sz,\n+\t\t\t.bar = NO_BAR,\n+\t\t\t.bar_offset = 0,\n+\t\t};\n+\t}\n+\n+\t/* One LL region per read channel */\n+\tfor (i = 0; i < edma->ll_rd_cnt; i++) {\n+\t\tif (!edma->ll_region_rd[i].sz)\n+\t\t\tcontinue;\n+\n+\t\tresources[idx++] = (struct pci_epc_aux_resource) {\n+\t\t\t.type = PCI_EPC_AUX_DMA_CHAN_DESC,\n+\t\t\t.phys_addr = edma->ll_region_rd[i].paddr,\n+\t\t\t.size = edma->ll_region_rd[i].sz,\n+\t\t\t.bar = NO_BAR,\n+\t\t\t.bar_offset = 0,\n+\t\t};\n+\t}\n+\n+\treturn idx;\n+}\n+\n static const struct pci_epc_ops epc_ops = {\n \t.write_header\t\t= dw_pcie_ep_write_header,\n \t.set_bar\t\t= dw_pcie_ep_set_bar,\n@@ -823,6 +973,7 @@ static const struct pci_epc_ops epc_ops = {\n \t.start\t\t\t= dw_pcie_ep_start,\n \t.stop\t\t\t= dw_pcie_ep_stop,\n \t.get_features\t\t= dw_pcie_ep_get_features,\n+\t.get_aux_resources\t= dw_pcie_ep_get_aux_resources,\n };\n \n /**\n","prefixes":["v9","3/7"]}