{"id":2197831,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2197831/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260218-phys_addr-v6-6-a603bf363218@rev.ng>","date":"2026-02-18T17:21:32","name":"[v6,6/7] hw/riscv: Set IOMMU PAS via property","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"0a035440bf3dbd1dcca72af154aeed2382b4f419","submitter":{"id":92408,"url":"http://patchwork.ozlabs.org/api/1.0/people/92408/?format=json","name":"Anton Johansson","email":"anjo@rev.ng"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260218-phys_addr-v6-6-a603bf363218@rev.ng/mbox/","series":[{"id":492577,"url":"http://patchwork.ozlabs.org/api/1.0/series/492577/?format=json","date":"2026-02-18T17:21:30","name":"single-binary: Drop TARGET_PHYS_ADDR_SPACE_BITS","version":6,"mbox":"http://patchwork.ozlabs.org/series/492577/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2197831/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n unprotected) header.d=rev.ng header.i=@rev.ng header.a=rsa-sha256\n header.s=dkim header.b=C/gJ8DR3;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Wed, 18 Feb 2026 12:18:55 -0500"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng;\n s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding:\n Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID:\n Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc\n :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe:\n List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post:\n List-Help; bh=LnNbdLp6lQkk91nnwZLN8LDmCRe89n2NmaZDvq59+QA=; b=C/gJ8DR3bhcrFV5\n keA9iPRwGad6D5iQaYFxDsA1NsTRDOzfqyhegk/4Qgw5fH/Cs3namKa9wnWwWR3VyI96nywOGBDMQ\n pqx1gk9X9YNmOjjfGAqZ77L2u7MMJgeY8GWdGZAxqdwWCaXrMJeBZjZq+limyBcNRLmiUZhXAu64n\n ec=;","Date":"Wed, 18 Feb 2026 18:21:32 +0100","Subject":"[PATCH v6 6/7] hw/riscv: Set IOMMU PAS via property","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260218-phys_addr-v6-6-a603bf363218@rev.ng>","References":"<20260218-phys_addr-v6-0-a603bf363218@rev.ng>","In-Reply-To":"<20260218-phys_addr-v6-0-a603bf363218@rev.ng>","To":"qemu-devel@nongnu.org","Cc":"=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ,\n Richard Henderson ,\n Helge Deller , Paolo Bonzini ,\n Song Gao , Bibo Mao ,\n Palmer Dabbelt ,\n Alistair Francis ,\n Brian Cain ,\n Chao Liu , Anton Johansson ","X-Developer-Signature":"v=1; a=ed25519-sha256; t=1771435335; l=4281;\n i=anjo@rev.ng; s=20260210; h=from:subject:message-id;\n bh=dlOqt+TTtplPC4FQ9ACzr9DxXad4u3ktCRVuu39x550=;\n b=THl3UN1A24W+CHvt1EgKc3BBOF0+bvJ1Mexi59eQOiaHaglsPzcRIiACJWHnyF+rVzH0Rso2f\n dI8C9OSBFMVBIpUarYR63houZRDezdgma+vpiktNiulLGqf+UA4x0VU","X-Developer-Key":"i=anjo@rev.ng; a=ed25519;\n pk=dKsZvj/g3kgDxnV1/SWg8a0YNGSpWtFGNsWIepQYKow=","Received-SPF":"pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng;\n helo=rev.ng","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Reply-to":"Anton Johansson ","From":"Anton Johansson via qemu development ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Replaces the only remaining use of TARGET_PHYS_ADDR_SPACE_BITS for RISCV\nwith a property RISCVIOMMUState::pas_bits that gets written to the\ncapabilities field upon device realization. This write needs to happen\nat realize-time to ensure the property has been set.\n\nFor the virt machine and sysbus device, pas_bits is set by\nvirt_machine_init() to either 34 or 56 bits, retaining previous behaviour.\nHowever, for the PCI device we do not have access to the CPU state, and\ninstead use the maximum riscv64 value of 56 bits.\n\nReviewed-by: Richard Henderson \nSigned-off-by: Anton Johansson \n---\n hw/riscv/riscv-iommu.h | 1 +\n hw/riscv/riscv-iommu-pci.c | 3 +++\n hw/riscv/riscv-iommu.c | 8 ++++----\n hw/riscv/virt.c | 7 +++++++\n 4 files changed, 15 insertions(+), 4 deletions(-)","diff":"diff --git a/hw/riscv/riscv-iommu.h b/hw/riscv/riscv-iommu.h\nindex 2dabd86941..2a9f6fccd5 100644\n--- a/hw/riscv/riscv-iommu.h\n+++ b/hw/riscv/riscv-iommu.h\n@@ -34,6 +34,7 @@ struct RISCVIOMMUState {\n /*< public >*/\n uint32_t version; /* Reported interface version number */\n uint32_t pid_bits; /* process identifier width */\n+ uint32_t pas_bits; /* physical address bits */\n uint32_t bus; /* PCI bus mapping for non-root endpoints */\n \n uint64_t cap; /* IOMMU supported capabilities */\ndiff --git a/hw/riscv/riscv-iommu-pci.c b/hw/riscv/riscv-iommu-pci.c\nindex 5f7d359204..14dd5f3857 100644\n--- a/hw/riscv/riscv-iommu-pci.c\n+++ b/hw/riscv/riscv-iommu-pci.c\n@@ -158,6 +158,9 @@ static void riscv_iommu_pci_init(Object *obj)\n \n iommu->icvec_avail_vectors = RISCV_IOMMU_PCI_ICVEC_VECTORS;\n riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_MSI);\n+\n+ /* Report maximum physical address size of riscv64 */\n+ iommu->pas_bits = 56;\n }\n \n static const Property riscv_iommu_pci_properties[] = {\ndiff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c\nindex b46b337375..98345b1280 100644\n--- a/hw/riscv/riscv-iommu.c\n+++ b/hw/riscv/riscv-iommu.c\n@@ -2453,10 +2453,6 @@ static void riscv_iommu_instance_init(Object *obj)\n /* Enable translation debug interface */\n s->cap = RISCV_IOMMU_CAP_DBG;\n \n- /* Report QEMU target physical address space limits */\n- s->cap = set_field(s->cap, RISCV_IOMMU_CAP_PAS,\n- TARGET_PHYS_ADDR_SPACE_BITS);\n-\n /* TODO: method to report supported PID bits */\n s->pid_bits = 8; /* restricted to size of MemTxAttrs.pid */\n s->cap |= RISCV_IOMMU_CAP_PD8;\n@@ -2487,6 +2483,9 @@ static void riscv_iommu_realize(DeviceState *dev, Error **errp)\n {\n RISCVIOMMUState *s = RISCV_IOMMU(dev);\n \n+ /* Report QEMU target physical address space limits. */\n+ s->cap = set_field(s->cap, RISCV_IOMMU_CAP_PAS, s->pas_bits);\n+\n s->cap |= s->version & RISCV_IOMMU_CAP_VERSION;\n if (s->enable_msi) {\n s->cap |= RISCV_IOMMU_CAP_MSI_FLAT | RISCV_IOMMU_CAP_MSI_MRIF;\n@@ -2645,6 +2644,7 @@ void riscv_iommu_reset(RISCVIOMMUState *s)\n static const Property riscv_iommu_properties[] = {\n DEFINE_PROP_UINT32(\"version\", RISCVIOMMUState, version,\n RISCV_IOMMU_SPEC_DOT_VER),\n+ DEFINE_PROP_UINT32(\"pas-bits\", RISCVIOMMUState, pas_bits, 0),\n DEFINE_PROP_UINT32(\"bus\", RISCVIOMMUState, bus, 0x0),\n DEFINE_PROP_UINT32(\"ioatc-limit\", RISCVIOMMUState, iot_limit,\n LIMIT_CACHE_IOT),\ndiff --git a/hw/riscv/virt.c b/hw/riscv/virt.c\nindex 07e66b3936..bbce2fb667 100644\n--- a/hw/riscv/virt.c\n+++ b/hw/riscv/virt.c\n@@ -1739,6 +1739,13 @@ static void virt_machine_init(MachineState *machine)\n object_property_set_link(OBJECT(iommu_sys), \"irqchip\",\n OBJECT(mmio_irqchip),\n &error_fatal);\n+ /*\n+ * For riscv64 use a physical address size of 56 bits (44 bit PPN),\n+ * and for riscv32 use 34 bits (22 bit PPN).\n+ */\n+ object_property_set_uint(OBJECT(iommu_sys), \"pas-bits\",\n+ riscv_is_32bit(&s->soc[0]) ? 34 : 56,\n+ &error_fatal);\n \n sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu_sys), &error_fatal);\n }\n","prefixes":["v6","6/7"]}