{"id":2197492,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2197492/?format=json","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.0/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260217-mtk-mt8189-clocks-v2-5-cd381cd05251@baylibre.com>","date":"2026-02-17T23:30:12","name":"[v2,5/7] clk: mediatek: add MUX_MIXED_CLR_SET_UPD_FLAGS() macro","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"4b090477b23421a9e5c85c1d64c409bd40ba4af2","submitter":{"id":87228,"url":"http://patchwork.ozlabs.org/api/1.0/people/87228/?format=json","name":"David Lechner","email":"dlechner@baylibre.com"},"delegate":{"id":3651,"url":"http://patchwork.ozlabs.org/api/1.0/users/3651/?format=json","username":"trini","first_name":"Tom","last_name":"Rini","email":"trini@ti.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260217-mtk-mt8189-clocks-v2-5-cd381cd05251@baylibre.com/mbox/","series":[{"id":492497,"url":"http://patchwork.ozlabs.org/api/1.0/series/492497/?format=json","date":"2026-02-17T23:30:08","name":"clk: mediatek: new mt8189 driver","version":2,"mbox":"http://patchwork.ozlabs.org/series/492497/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2197492/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=baylibre-com.20230601.gappssmtp.com\n header.i=@baylibre-com.20230601.gappssmtp.com header.a=rsa-sha256\n header.s=20230601 header.b=iY8HqvPP;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260217-mtk-mt8189-clocks-v2-5-cd381cd05251@baylibre.com>","References":"<20260217-mtk-mt8189-clocks-v2-0-cd381cd05251@baylibre.com>","In-Reply-To":"<20260217-mtk-mt8189-clocks-v2-0-cd381cd05251@baylibre.com>","To":"Lukasz Majewski , Ryder Lee ,\n Weijie Gao ,\n Chunfeng Yun ,\n Igor Belwon ,\n GSS_MTK_Uboot_upstream ,\n Tom Rini ","Cc":"Julien Stephan , u-boot@lists.denx.de,\n David Lechner ","X-Mailer":"b4 0.14.3","X-Developer-Signature":"v=1; a=openpgp-sha256; l=1350; i=dlechner@baylibre.com;\n h=from:subject:message-id;\n bh=+r3Mtaip08VF+oET76BCWEanas4FlGfdK9u8ImuiBEI=;\n b=owEBhAF7/pANAwAKAcLMIAH/AY/AAcsmYgBplPoq5eTcyM/ctjX8Rj5VOz+n9/IT7fLo4Ac9X\n WvHododzieJAUoEAAEKADQWIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaZT6KhYcZGxlY2huZXJA\n YmF5bGlicmUuY29tAAoJEMLMIAH/AY/AiskH/1hAe7hweMcJ1MzdO83aIM1JIbYTQAWPU44VVpj\n usQDFClmu++cKK1auRO7mKgxSJQY0oFrkj1CuR7BUbQUopfLFbkfiehaqrpYB7rj6CrvItj/KcL\n NQypIh3N3xJVgLIYDN33yrcg2C5mV+aEKddSN3Hd9GK7SRP/SIOkQLQe2caCSgvWceicrt+UsC7\n WZpd9rueFHkht8wlSagS+jElYvFT+nFyqSzFE9gYbed2DjWCWhqwzj2Rrr0ZBYnkJtzpyO8ikL+\n ViROjyaMNZr/SEORHF2JoEA4gpTR2t1iM1WP8pBIerOuP76pR4vJsQZRGco4Gq4BggnLKJ7jDgT\n oqIo=","X-Developer-Key":"i=dlechner@baylibre.com; a=openpgp;\n fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"Add a new MUX_MIXED_CLR_SET_UPD_FLAGS() macro. This is the same as\nMUX_CLR_SET_UPD_FLAGS() except that it uses the parent_flags member\nof the union instead of parent.\n\nThis will be needed by the incoming mt8189 clock driver.\n\nSigned-off-by: David Lechner \n---\n drivers/clk/mediatek/clk-mtk.h | 18 ++++++++++++++++++\n 1 file changed, 18 insertions(+)","diff":"diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h\nindex c6874445dbe..c4aeee49abd 100644\n--- a/drivers/clk/mediatek/clk-mtk.h\n+++ b/drivers/clk/mediatek/clk-mtk.h\n@@ -221,6 +221,24 @@ struct mtk_composite {\n \t\t.flags = _flags,\t\t\t\t\t\\\n \t}\n \n+#define MUX_MIXED_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs,\\\n+\t\t\t\t _mux_clr_ofs, _shift, _width, _gate,\\\n+\t\t\t\t _upd_ofs, _upd, _flags) {\t\t\\\n+\t\t.id = _id,\t\t\t\t\t\t\\\n+\t\t.mux_reg = _mux_ofs,\t\t\t\t\t\\\n+\t\t.mux_set_reg = _mux_set_ofs,\t\t\t\t\\\n+\t\t.mux_clr_reg = _mux_clr_ofs,\t\t\t\t\\\n+\t\t.upd_reg = _upd_ofs,\t\t\t\t\t\\\n+\t\t.upd_shift = _upd,\t\t\t\t\t\\\n+\t\t.mux_shift = _shift,\t\t\t\t\t\\\n+\t\t.mux_mask = BIT(_width) - 1,\t\t\t\t\\\n+\t\t.gate_reg = _mux_ofs,\t\t\t\t\t\\\n+\t\t.gate_shift = _gate,\t\t\t\t\t\\\n+\t\t.parent_flags = _parents,\t\t\t\t\\\n+\t\t.num_parents = ARRAY_SIZE(_parents),\t\t\t\\\n+\t\t.flags = CLK_PARENT_MIXED | (_flags),\t\t\t\\\n+\t}\n+\n struct mtk_gate_regs {\n \tu32 sta_ofs;\n \tu32 clr_ofs;\n","prefixes":["v2","5/7"]}