{"id":2197491,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2197491/?format=json","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.0/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260217-mtk-mt8189-clocks-v2-3-cd381cd05251@baylibre.com>","date":"2026-02-17T23:30:10","name":"[v2,3/7] clk: mediatek: add mtk_clk_id_is_* helper functions","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"01d04fae3445c6b57c02f4c068cd4dfdd2f0342f","submitter":{"id":87228,"url":"http://patchwork.ozlabs.org/api/1.0/people/87228/?format=json","name":"David Lechner","email":"dlechner@baylibre.com"},"delegate":{"id":3651,"url":"http://patchwork.ozlabs.org/api/1.0/users/3651/?format=json","username":"trini","first_name":"Tom","last_name":"Rini","email":"trini@ti.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260217-mtk-mt8189-clocks-v2-3-cd381cd05251@baylibre.com/mbox/","series":[{"id":492497,"url":"http://patchwork.ozlabs.org/api/1.0/series/492497/?format=json","date":"2026-02-17T23:30:08","name":"clk: mediatek: new mt8189 driver","version":2,"mbox":"http://patchwork.ozlabs.org/series/492497/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2197491/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=baylibre-com.20230601.gappssmtp.com\n header.i=@baylibre-com.20230601.gappssmtp.com header.a=rsa-sha256\n header.s=20230601 header.b=GGNrkQAj;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260217-mtk-mt8189-clocks-v2-3-cd381cd05251@baylibre.com>","References":"<20260217-mtk-mt8189-clocks-v2-0-cd381cd05251@baylibre.com>","In-Reply-To":"<20260217-mtk-mt8189-clocks-v2-0-cd381cd05251@baylibre.com>","To":"Lukasz Majewski , Ryder Lee ,\n Weijie Gao ,\n Chunfeng Yun ,\n Igor Belwon ,\n GSS_MTK_Uboot_upstream ,\n Tom Rini ","Cc":"Julien Stephan , u-boot@lists.denx.de,\n David Lechner ","X-Mailer":"b4 0.14.3","X-Developer-Signature":"v=1; a=openpgp-sha256; l=9958; i=dlechner@baylibre.com;\n h=from:subject:message-id;\n bh=rQtZzGMOm61RptZkKnMBsoG1ARBDiNoGJZyL1uCk2Gs=;\n b=owEBhAF7/pANAwAKAcLMIAH/AY/AAcsmYgBplPodvV3UPgpxexZbKOTpIbqQc47zWXRZm1ab/\n IoHAAX10guJAUoEAAEKADQWIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaZT6HRYcZGxlY2huZXJA\n YmF5bGlicmUuY29tAAoJEMLMIAH/AY/ABFEH/3hNp+xolEhmrZUzW5iDUO0hU+DoQIxtu8Txp4A\n mklKjwwuxQnVBjNqAXAXW3AQqmWPIG1meWxJYzCopLFVwr/UrT9brMVwtULwuP8kuk/tK236IJb\n qBpE+8nK1DqsAZidnsuze1mnAE4+YHNY+Q68XerGDnaqlrfBigu/qY+vrt0zO1JuCkZl7dm+9P3\n fiZdRrqApdcWV/EL02Jjisu4Qzu+JnYvjkVXftOTXwxAcKjZ9n2B8tOuyT01L5MDlB8lsbYQP0Z\n LVrd6lYAUq5y0r+ThNGntcctNkbJSGia/petjReJRaa/R1Jo2rbLRF+L5KhgZKzNNzEFu9fFAYU\n x4QI=","X-Developer-Key":"i=dlechner@baylibre.com; a=openpgp;\n fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"Add helper functions to check if a clock ID corresponds to a particular\nclock type (mux, gate, fdiv). This simplifies the code and makes it more\nreadable.\n\nAdditionally, it removes the restriction that fdivs_offs < muxes_offs <\ngates_offs by making the checking more strict in some places. This will\nallow future drivers to not have to define a mapping to meet this\nrequirement.\n\nSigned-off-by: David Lechner \n---\n drivers/clk/mediatek/clk-mtk.c | 128 ++++++++++++++++++++---------------------\n 1 file changed, 64 insertions(+), 64 deletions(-)","diff":"diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c\nindex 0123b0ce7b1..3bd9021b9cf 100644\n--- a/drivers/clk/mediatek/clk-mtk.c\n+++ b/drivers/clk/mediatek/clk-mtk.c\n@@ -85,6 +85,34 @@ static int mtk_common_clk_get_unmapped_id(struct clk *clk)\n \treturn -ENOENT;\n }\n \n+static bool mtk_clk_id_is_pll(const struct mtk_clk_tree *tree, int mapped_id)\n+{\n+\treturn tree->plls && mapped_id < tree->num_plls;\n+}\n+\n+static bool mtk_clk_id_is_fclk(const struct mtk_clk_tree *tree, int mapped_id)\n+{\n+\treturn tree->fclks && mapped_id < tree->num_fclks;\n+}\n+\n+static bool mtk_clk_id_is_fdiv(const struct mtk_clk_tree *tree, int mapped_id)\n+{\n+\treturn tree->fdivs && mapped_id >= tree->fdivs_offs &&\n+\t mapped_id < tree->fdivs_offs + tree->num_fdivs;\n+}\n+\n+static bool mtk_clk_id_is_mux(const struct mtk_clk_tree *tree, int mapped_id)\n+{\n+\treturn tree->muxes && mapped_id >= tree->muxes_offs &&\n+\t mapped_id < tree->muxes_offs + tree->num_muxes;\n+}\n+\n+static bool mtk_clk_id_is_gate(const struct mtk_clk_tree *tree, int mapped_id)\n+{\n+\treturn tree->gates && mapped_id >= tree->gates_offs &&\n+\t mapped_id < tree->gates_offs + tree->num_gates;\n+}\n+\n static int mtk_dummy_enable(struct clk *clk)\n {\n \treturn 0;\n@@ -375,15 +403,10 @@ static const int mtk_apmixedsys_of_xlate(struct clk *clk,\n \t\treturn ret;\n \n \t/* apmixedsys only uses plls and gates. */\n+\tif (!mtk_clk_id_is_pll(tree, clk->id) && !mtk_clk_id_is_gate(tree, clk->id))\n+\t\treturn -ENOENT;\n \n-\tif (tree->plls && clk->id < tree->num_plls)\n-\t\treturn 0;\n-\n-\tif (tree->gates && clk->id >= tree->gates_offs &&\n-\t clk->id < tree->gates_offs + tree->num_gates)\n-\t\treturn 0;\n-\n-\treturn -ENOENT;\n+\treturn 0;\n }\n \n static unsigned long __mtk_pll_recalc_rate(const struct mtk_pll_data *pll,\n@@ -497,7 +520,7 @@ static ulong mtk_apmixedsys_set_rate(struct clk *clk, ulong rate)\n \tu32 pcw = 0;\n \tu32 postdiv;\n \n-\tif (priv->tree->gates && clk->id >= priv->tree->gates_offs)\n+\tif (!mtk_clk_id_is_pll(priv->tree, clk->id))\n \t\treturn -EINVAL;\n \n \tmtk_pll_calc_values(priv, clk->id, &pcw, &postdiv, rate);\n@@ -515,7 +538,7 @@ static ulong mtk_apmixedsys_get_rate(struct clk *clk)\n \tu32 pcw;\n \n \t/* GATE handling */\n-\tif (priv->tree->gates && clk->id >= priv->tree->gates_offs) {\n+\tif (mtk_clk_id_is_gate(priv->tree, clk->id)) {\n \t\tgate = &priv->tree->gates[clk->id - priv->tree->gates_offs];\n \t\treturn mtk_clk_find_parent_rate(clk, gate->parent, NULL);\n \t}\n@@ -541,7 +564,7 @@ static int mtk_apmixedsys_enable(struct clk *clk)\n \tu32 r;\n \n \t/* GATE handling */\n-\tif (priv->tree->gates && clk->id >= priv->tree->gates_offs) {\n+\tif (mtk_clk_id_is_gate(priv->tree, clk->id)) {\n \t\tgate = &priv->tree->gates[clk->id - priv->tree->gates_offs];\n \t\treturn mtk_gate_enable(priv->base, gate);\n \t}\n@@ -579,7 +602,7 @@ static int mtk_apmixedsys_disable(struct clk *clk)\n \tu32 r;\n \n \t/* GATE handling */\n-\tif (priv->tree->gates && clk->id >= priv->tree->gates_offs) {\n+\tif (mtk_clk_id_is_gate(priv->tree, clk->id)) {\n \t\tgate = &priv->tree->gates[clk->id - priv->tree->gates_offs];\n \t\treturn mtk_gate_disable(priv->base, gate);\n \t}\n@@ -649,23 +672,11 @@ static const int mtk_topckgen_of_xlate(struct clk *clk,\n \t\treturn ret;\n \n \t/* topckgen only uses fclks, fdivs, muxes and gates. */\n+\tif (!mtk_clk_id_is_fclk(tree, clk->id) && !mtk_clk_id_is_fdiv(tree, clk->id) &&\n+\t !mtk_clk_id_is_mux(tree, clk->id) && !mtk_clk_id_is_gate(tree, clk->id))\n+\t\treturn -ENOENT;\n \n-\tif (tree->fclks && clk->id < tree->num_fclks)\n-\t\treturn 0;\n-\n-\tif (tree->fdivs && clk->id >= tree->fdivs_offs &&\n-\t clk->id < tree->fdivs_offs + tree->num_fdivs)\n-\t\treturn 0;\n-\n-\tif (tree->muxes && clk->id >= tree->muxes_offs &&\n-\t clk->id < tree->muxes_offs + tree->num_muxes)\n-\t\treturn 0;\n-\n-\tif (tree->gates && clk->id >= tree->gates_offs &&\n-\t clk->id < tree->gates_offs + tree->num_gates)\n-\t\treturn 0;\n-\n-\treturn -ENOENT;\n+\treturn 0;\n }\n \n static ulong mtk_factor_recalc_rate(const struct mtk_fixed_factor *fdiv,\n@@ -723,21 +734,22 @@ static ulong mtk_topckgen_get_rate(struct clk *clk)\n \tstruct mtk_clk_priv *priv = dev_get_priv(clk->dev);\n \tconst struct mtk_clk_tree *tree = priv->tree;\n \n-\tif (tree->gates && clk->id >= tree->gates_offs &&\n-\t clk->id < tree->gates_offs + tree->num_gates) {\n+\tif (mtk_clk_id_is_fclk(tree, clk->id))\n+\t\treturn tree->fclks[clk->id].rate;\n+\n+\tif (mtk_clk_id_is_fdiv(tree, clk->id))\n+\t\treturn mtk_topckgen_get_factor_rate(clk, clk->id - tree->fdivs_offs);\n+\n+\tif (mtk_clk_id_is_mux(tree, clk->id))\n+\t\treturn mtk_topckgen_get_mux_rate(clk, clk->id - tree->muxes_offs);\n+\n+\tif (mtk_clk_id_is_gate(tree, clk->id)) {\n \t\tconst struct mtk_gate *gate = &tree->gates[clk->id - tree->gates_offs];\n \n \t\treturn mtk_clk_find_parent_rate(clk, gate->parent, NULL);\n \t}\n \n-\tif (clk->id < priv->tree->fdivs_offs)\n-\t\treturn priv->tree->fclks[clk->id].rate;\n-\telse if (clk->id < priv->tree->muxes_offs)\n-\t\treturn mtk_topckgen_get_factor_rate(clk, clk->id -\n-\t\t\t\t\t\t priv->tree->fdivs_offs);\n-\telse\n-\t\treturn mtk_topckgen_get_mux_rate(clk, clk->id -\n-\t\t\t\t\t\t priv->tree->muxes_offs);\n+\treturn -ENOENT;\n }\n \n static int mtk_clk_mux_enable(struct clk *clk)\n@@ -746,7 +758,7 @@ static int mtk_clk_mux_enable(struct clk *clk)\n \tconst struct mtk_composite *mux;\n \tu32 val;\n \n-\tif (clk->id < priv->tree->muxes_offs)\n+\tif (!mtk_clk_id_is_mux(priv->tree, clk->id))\n \t\treturn 0;\n \n \tmux = &priv->tree->muxes[clk->id - priv->tree->muxes_offs];\n@@ -778,8 +790,7 @@ static int mtk_topckgen_enable(struct clk *clk)\n \tstruct mtk_clk_priv *priv = dev_get_priv(clk->dev);\n \tconst struct mtk_clk_tree *tree = priv->tree;\n \n-\tif (tree->gates && clk->id >= tree->gates_offs &&\n-\t clk->id < tree->gates_offs + tree->num_gates) {\n+\tif (mtk_clk_id_is_gate(tree, clk->id)) {\n \t\tconst struct mtk_gate *gate = &tree->gates[clk->id - tree->gates_offs];\n \n \t\treturn mtk_gate_enable(priv->base, gate);\n@@ -794,7 +805,7 @@ static int mtk_clk_mux_disable(struct clk *clk)\n \tconst struct mtk_composite *mux;\n \tu32 val;\n \n-\tif (clk->id < priv->tree->muxes_offs)\n+\tif (!mtk_clk_id_is_mux(priv->tree, clk->id))\n \t\treturn 0;\n \n \tmux = &priv->tree->muxes[clk->id - priv->tree->muxes_offs];\n@@ -819,8 +830,7 @@ static int mtk_topckgen_disable(struct clk *clk)\n \tstruct mtk_clk_priv *priv = dev_get_priv(clk->dev);\n \tconst struct mtk_clk_tree *tree = priv->tree;\n \n-\tif (tree->gates && clk->id >= tree->gates_offs &&\n-\t clk->id < tree->gates_offs + tree->num_gates) {\n+\tif (mtk_clk_id_is_gate(tree, clk->id)) {\n \t\tconst struct mtk_gate *gate = &tree->gates[clk->id - tree->gates_offs];\n \n \t\treturn mtk_gate_disable(priv->base, gate);\n@@ -836,8 +846,7 @@ static int mtk_common_clk_set_parent(struct clk *clk, struct clk *parent)\n \tint parent_unmapped_id;\n \tu32 parent_type;\n \n-\tif (!priv->tree->muxes || clk->id < priv->tree->muxes_offs ||\n-\t clk->id >= priv->tree->muxes_offs + priv->tree->num_muxes)\n+\tif (!mtk_clk_id_is_mux(priv->tree, clk->id))\n \t\treturn 0;\n \n \tif (!parent_priv)\n@@ -917,20 +926,11 @@ static const int mtk_infrasys_of_xlate(struct clk *clk,\n \t\treturn ret;\n \n \t/* ifrasys only uses fdivs, muxes and gates. */\n+\tif (!mtk_clk_id_is_fdiv(tree, clk->id) && !mtk_clk_id_is_mux(tree, clk->id) &&\n+\t !mtk_clk_id_is_gate(tree, clk->id))\n+\t\treturn -ENOENT;\n \n-\tif (tree->fdivs && clk->id >= tree->fdivs_offs &&\n-\t clk->id < tree->fdivs_offs + tree->num_fdivs)\n-\t\treturn 0;\n-\n-\tif (tree->muxes && clk->id >= tree->muxes_offs &&\n-\t clk->id < tree->muxes_offs + tree->num_muxes)\n-\t\treturn 0;\n-\n-\tif (tree->gates && clk->id >= tree->gates_offs &&\n-\t clk->id < tree->gates_offs + tree->num_gates)\n-\t\treturn 0;\n-\n-\treturn -ENOENT;\n+\treturn 0;\n }\n \n static int mtk_clk_infrasys_enable(struct clk *clk)\n@@ -939,7 +939,7 @@ static int mtk_clk_infrasys_enable(struct clk *clk)\n \tconst struct mtk_gate *gate;\n \n \t/* MUX handling */\n-\tif (!priv->tree->gates || clk->id < priv->tree->gates_offs)\n+\tif (!mtk_clk_id_is_gate(priv->tree, clk->id))\n \t\treturn mtk_clk_mux_enable(clk);\n \n \tgate = &priv->tree->gates[clk->id - priv->tree->gates_offs];\n@@ -952,7 +952,7 @@ static int mtk_clk_infrasys_disable(struct clk *clk)\n \tconst struct mtk_gate *gate;\n \n \t/* MUX handling */\n-\tif (!priv->tree->gates || clk->id < priv->tree->gates_offs)\n+\tif (!mtk_clk_id_is_gate(priv->tree, clk->id))\n \t\treturn mtk_clk_mux_disable(clk);\n \n \tgate = &priv->tree->gates[clk->id - priv->tree->gates_offs];\n@@ -1004,13 +1004,13 @@ static ulong mtk_infrasys_get_rate(struct clk *clk)\n \tstruct mtk_clk_priv *priv = dev_get_priv(clk->dev);\n \tulong rate;\n \n-\tif (clk->id < priv->tree->fdivs_offs) {\n+\tif (mtk_clk_id_is_fclk(priv->tree, clk->id)) {\n \t\trate = priv->tree->fclks[clk->id].rate;\n-\t} else if (clk->id < priv->tree->muxes_offs) {\n+\t} else if (mtk_clk_id_is_fdiv(priv->tree, clk->id)) {\n \t\trate = mtk_infrasys_get_factor_rate(clk, clk->id -\n \t\t\t\t\t\t priv->tree->fdivs_offs);\n \t/* No gates defined or ID is a MUX */\n-\t} else if (!priv->tree->gates || clk->id < priv->tree->gates_offs) {\n+\t} else if (!mtk_clk_id_is_gate(priv->tree, clk->id)) {\n \t\trate = mtk_infrasys_get_mux_rate(clk, clk->id -\n \t\t\t\t\t\t priv->tree->muxes_offs);\n \t/* Only valid with muxes + gates implementation */\n","prefixes":["v2","3/7"]}