{"id":2197490,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2197490/?format=json","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.0/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260217-mtk-mt8189-clocks-v2-4-cd381cd05251@baylibre.com>","date":"2026-02-17T23:30:11","name":"[v2,4/7] clk: mediatek: add CLK_PARENT_EXT","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"6043ecae9a3db6c1d19446b7b29a17ee2c8117a1","submitter":{"id":87228,"url":"http://patchwork.ozlabs.org/api/1.0/people/87228/?format=json","name":"David Lechner","email":"dlechner@baylibre.com"},"delegate":{"id":3651,"url":"http://patchwork.ozlabs.org/api/1.0/users/3651/?format=json","username":"trini","first_name":"Tom","last_name":"Rini","email":"trini@ti.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260217-mtk-mt8189-clocks-v2-4-cd381cd05251@baylibre.com/mbox/","series":[{"id":492497,"url":"http://patchwork.ozlabs.org/api/1.0/series/492497/?format=json","date":"2026-02-17T23:30:08","name":"clk: mediatek: new mt8189 driver","version":2,"mbox":"http://patchwork.ozlabs.org/series/492497/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2197490/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=baylibre-com.20230601.gappssmtp.com\n header.i=@baylibre-com.20230601.gappssmtp.com header.a=rsa-sha256\n header.s=20230601 header.b=ZUAAqKG0;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260217-mtk-mt8189-clocks-v2-4-cd381cd05251@baylibre.com>","References":"<20260217-mtk-mt8189-clocks-v2-0-cd381cd05251@baylibre.com>","In-Reply-To":"<20260217-mtk-mt8189-clocks-v2-0-cd381cd05251@baylibre.com>","To":"Lukasz Majewski , Ryder Lee ,\n Weijie Gao ,\n Chunfeng Yun ,\n Igor Belwon ,\n GSS_MTK_Uboot_upstream ,\n Tom Rini ","Cc":"Julien Stephan , u-boot@lists.denx.de,\n David Lechner ","X-Mailer":"b4 0.14.3","X-Developer-Signature":"v=1; a=openpgp-sha256; l=3908; i=dlechner@baylibre.com;\n h=from:subject:message-id;\n bh=72FAPUqL2IKBdswijnUNc/k57fkdXxHVkljNwK2s+1o=;\n b=owEBhAF7/pANAwAKAcLMIAH/AY/AAcsmYgBplPojYFUP4h+/cIzbvKIl1XzQru16JYMAoGEkJ\n Wu3ivViZNuJAUoEAAEKADQWIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaZT6IxYcZGxlY2huZXJA\n YmF5bGlicmUuY29tAAoJEMLMIAH/AY/A6oAIAIF55F2pfFjTPEqxAuJ7dtySBnGdRHFxzS4oOh0\n yy582fI844gA2Q1gTxU1HoiecHWRxAkM7TNTAaOxNVFjAj6gukJq0P5zlgKO5cNwibo8hyO0xEj\n 5BWd2eUrJisjfqcR76feaHHl2PSAu2Keto8vznQo8ABCzGe2LM6Rm0VzFvw0O+EY6VH6OlUY1DA\n PUqOy5E9HSxs6E52yg27CcPVoGItAJgU9vZVjd0CB7Aj7ZrCw+wmVGMGFBGHF608fauMjVOgLSb\n zlNOwr9ZL8OVhoL3pYzcZD/fs9umj1eayH/p9DqPcQUnjM/OG0cjJlaUweGbu6LOuHV7GPPyV06\n xglY=","X-Developer-Key":"i=dlechner@baylibre.com; a=openpgp;\n fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"Add support for external clock parent type in MediaTek clock driver to\nallow multiple external clock sources.\n\nThis is intended to eventually replace CLK_PARENT_XTAL which only allows\na single external clock source. Replacing CLK_PARENT_XTAL is not trivial\nsince it would required touching all chip-specific drivers. So that is\nsaved for another day.\n\nBefore this change, the only way to add additional external clocks was\nto use a clock ID mapping and add the external clock in the fixed clocks\nportion of the CLK_PARENT_TOPCKGEN clocks. After this change, such hacks\nare no longer necessary and external clocks can be added in a cleaner\nway.\n\nSigned-off-by: David Lechner \n---\n drivers/clk/mediatek/clk-mtk.c | 17 +++++++++++++++++\n drivers/clk/mediatek/clk-mtk.h | 8 ++++++--\n 2 files changed, 23 insertions(+), 2 deletions(-)","diff":"diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c\nindex 3bd9021b9cf..6f7e2144332 100644\n--- a/drivers/clk/mediatek/clk-mtk.c\n+++ b/drivers/clk/mediatek/clk-mtk.c\n@@ -168,6 +168,14 @@ static int mtk_gate_disable(void __iomem *base, const struct mtk_gate *gate)\n \treturn 0;\n }\n \n+static ulong mtk_ext_clock_get_rate(const struct mtk_clk_tree *tree, int id)\n+{\n+\tif (!tree->ext_clk_rates || id >= tree->num_ext_clks)\n+\t\treturn -ENOENT;\n+\n+\treturn tree->ext_clk_rates[id];\n+}\n+\n /*\n * In case the rate change propagation to parent clocks is undesirable,\n * this function is recursively called to find the parent to calculate\n@@ -235,6 +243,8 @@ static ulong mtk_find_parent_rate(struct mtk_clk_priv *priv, struct clk *clk,\n \t\tbreak;\n \tcase CLK_PARENT_XTAL:\n \t\treturn priv->tree->xtal_rate;\n+\tcase CLK_PARENT_EXT:\n+\t\treturn mtk_ext_clock_get_rate(priv->tree, parent);\n \tdefault:\n \t\tparent_dev = NULL;\n \t\tbreak;\n@@ -337,6 +347,9 @@ static void mtk_clk_print_parent(const char *prefix, int parent, u32 flags)\n \tcase CLK_PARENT_XTAL:\n \t\tparent_type_str = \"xtal\";\n \t\tbreak;\n+\tcase CLK_PARENT_EXT:\n+\t\tparent_type_str = \"ext\";\n+\t\tbreak;\n \tcase CLK_PARENT_MIXED:\n \t\tparent_type_str = \"mixed\";\n \t\tbreak;\n@@ -1027,6 +1040,8 @@ static ulong mtk_infrasys_get_rate(struct clk *clk)\n \t\t */\n \t\telse if (gate->flags & CLK_PARENT_XTAL)\n \t\t\treturn priv->tree->xtal_rate;\n+\t\telse if (gate->flags & CLK_PARENT_EXT)\n+\t\t\treturn mtk_ext_clock_get_rate(priv->tree, gate->parent);\n \n \t\trate = mtk_clk_find_parent_rate(clk, gate->parent, parent);\n \t}\n@@ -1143,6 +1158,8 @@ static ulong mtk_clk_gate_get_rate(struct clk *clk)\n \t */\n \t} else if (gate->flags & CLK_PARENT_XTAL) {\n \t\treturn priv->tree->xtal_rate;\n+\t} else if (gate->flags & CLK_PARENT_EXT) {\n+\t\treturn mtk_ext_clock_get_rate(priv->tree, gate->parent);\n \t}\n \n \treturn mtk_clk_find_parent_rate(clk, gate->parent, parent);\ndiff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h\nindex f3d2377aee4..c6874445dbe 100644\n--- a/drivers/clk/mediatek/clk-mtk.h\n+++ b/drivers/clk/mediatek/clk-mtk.h\n@@ -34,12 +34,13 @@\n #define CLK_PARENT_TOPCKGEN\t\tBIT(5)\n #define CLK_PARENT_INFRASYS\t\tBIT(6)\n #define CLK_PARENT_XTAL\t\t\tBIT(7)\n+#define CLK_PARENT_EXT\t\t\tBIT(8)\n /*\n * For CLK_PARENT_MIXED to correctly work, is required to\n * define in clk_tree flags the clk type using the alias.\n */\n-#define CLK_PARENT_MIXED\t\tBIT(8)\n-#define CLK_PARENT_MASK\t\t\tGENMASK(8, 4)\n+#define CLK_PARENT_MIXED\t\tBIT(9)\n+#define CLK_PARENT_MASK\t\t\tGENMASK(9, 4)\n \n #define ETHSYS_HIFSYS_RST_CTRL_OFS\t0x34\n \n@@ -255,6 +256,9 @@ struct mtk_gate {\n struct mtk_clk_tree {\n \tunsigned long xtal_rate;\n \tunsigned long xtal2_rate;\n+\t/* External fixed clocks - excluded from mapping. */\n+\tconst ulong *ext_clk_rates;\n+\tconst int num_ext_clks;\n \t/*\n \t * Clock IDs may be remapped with an auxiliary table. Enable this by\n \t * defining .id_offs_map and .id_offs_map_size. This is needed e.g. when\n","prefixes":["v2","4/7"]}