{"id":2197385,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2197385/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260217212245.95321-2-ltaylorsimpson@gmail.com>","date":"2026-02-17T21:22:38","name":"[v3,1/8] Hexagon (target/hexagon) Properly handle Hexagon CPU version","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"8fd83fb43796f481e7e57904a8279947ce594885","submitter":{"id":86757,"url":"http://patchwork.ozlabs.org/api/1.0/people/86757/?format=json","name":"Taylor Simpson","email":"ltaylorsimpson@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260217212245.95321-2-ltaylorsimpson@gmail.com/mbox/","series":[{"id":492479,"url":"http://patchwork.ozlabs.org/api/1.0/series/492479/?format=json","date":"2026-02-17T21:22:40","name":"Hexagon (target/hexagon) Check opcodes versions","version":3,"mbox":"http://patchwork.ozlabs.org/series/492479/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2197385/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=IwHKfcBD;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fFt0s5qGVz1xwC\n\tfor ; Wed, 18 Feb 2026 08:23:25 +1100 (AEDT)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1vsSWz-0002OR-IU; Tue, 17 Feb 2026 16:22:53 -0500","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1vsSWy-0002Kw-OR\n for qemu-devel@nongnu.org; Tue, 17 Feb 2026 16:22:52 -0500","from mail-oi1-x230.google.com ([2607:f8b0:4864:20::230])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1vsSWx-0002Gh-1h\n for qemu-devel@nongnu.org; Tue, 17 Feb 2026 16:22:52 -0500","by mail-oi1-x230.google.com with SMTP id\n 5614622812f47-45f04f1348cso3112210b6e.1\n for ; Tue, 17 Feb 2026 13:22:50 -0800 (PST)","from taylor-ubuntu.. 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-0700","Message-ID":"<20260217212245.95321-2-ltaylorsimpson@gmail.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260217212245.95321-1-ltaylorsimpson@gmail.com>","References":"<20260217212245.95321-1-ltaylorsimpson@gmail.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::230;\n envelope-from=ltaylorsimpson@gmail.com; helo=mail-oi1-x230.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Add the following CPU versions that were previously missing\n v5\n v55\n v60\n v61\n v62\n v65\n\nCreate a CPUHexagonDef struct to represent the definition of a core\n Currently contains an enum with the known Hexagon CPU versions\nAdd a field to HexagonCPUClass to note the Hexagon definition\n\nCo-authored-by: Matheus Tavares Bernardino \nCo-authored-by: Brian Cain \nSigned-off-by: Taylor Simpson \n---\n target/hexagon/cpu-qom.h | 27 +++++++++++++++++++++++\n target/hexagon/cpu.h | 2 ++\n target/hexagon/cpu.c | 46 ++++++++++++++++++++++++----------------\n 3 files changed, 57 insertions(+), 18 deletions(-)","diff":"diff --git a/target/hexagon/cpu-qom.h b/target/hexagon/cpu-qom.h\nindex 0b149bd5fe..6e1bb04070 100644\n--- a/target/hexagon/cpu-qom.h\n+++ b/target/hexagon/cpu-qom.h\n@@ -11,11 +11,38 @@\n \n #include \"hw/core/cpu.h\"\n \n+typedef enum {\n+ HEX_VER_NONE = 0x00,\n+ HEX_VER_V5 = 0x04,\n+ HEX_VER_V55 = 0x05,\n+ HEX_VER_V60 = 0x60,\n+ HEX_VER_V61 = 0x61,\n+ HEX_VER_V62 = 0x62,\n+ HEX_VER_V65 = 0x65,\n+ HEX_VER_V66 = 0x66,\n+ HEX_VER_V67 = 0x67,\n+ HEX_VER_V68 = 0x68,\n+ HEX_VER_V69 = 0x69,\n+ HEX_VER_V71 = 0x71,\n+ HEX_VER_V73 = 0x73,\n+ HEX_VER_ANY = 0xff,\n+} HexagonVersion;\n+\n+typedef struct {\n+ HexagonVersion hex_version;\n+} HexagonCPUDef;\n+\n #define TYPE_HEXAGON_CPU \"hexagon-cpu\"\n \n #define HEXAGON_CPU_TYPE_SUFFIX \"-\" TYPE_HEXAGON_CPU\n #define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX)\n \n+#define TYPE_HEXAGON_CPU_V5 HEXAGON_CPU_TYPE_NAME(\"v5\")\n+#define TYPE_HEXAGON_CPU_V55 HEXAGON_CPU_TYPE_NAME(\"v55\")\n+#define TYPE_HEXAGON_CPU_V60 HEXAGON_CPU_TYPE_NAME(\"v60\")\n+#define TYPE_HEXAGON_CPU_V61 HEXAGON_CPU_TYPE_NAME(\"v61\")\n+#define TYPE_HEXAGON_CPU_V62 HEXAGON_CPU_TYPE_NAME(\"v62\")\n+#define TYPE_HEXAGON_CPU_V65 HEXAGON_CPU_TYPE_NAME(\"v65\")\n #define TYPE_HEXAGON_CPU_V66 HEXAGON_CPU_TYPE_NAME(\"v66\")\n #define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME(\"v67\")\n #define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME(\"v68\")\ndiff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h\nindex 85afd59277..f99647dfb6 100644\n--- a/target/hexagon/cpu.h\n+++ b/target/hexagon/cpu.h\n@@ -117,6 +117,8 @@ typedef struct HexagonCPUClass {\n \n DeviceRealize parent_realize;\n ResettablePhases parent_phases;\n+\n+ const HexagonCPUDef *hex_def;\n } HexagonCPUClass;\n \n struct ArchCPU {\ndiff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c\nindex 58a22ee41f..949d509a15 100644\n--- a/target/hexagon/cpu.c\n+++ b/target/hexagon/cpu.c\n@@ -27,13 +27,6 @@\n #include \"exec/gdbstub.h\"\n #include \"accel/tcg/cpu-ops.h\"\n \n-static void hexagon_v66_cpu_init(Object *obj) { }\n-static void hexagon_v67_cpu_init(Object *obj) { }\n-static void hexagon_v68_cpu_init(Object *obj) { }\n-static void hexagon_v69_cpu_init(Object *obj) { }\n-static void hexagon_v71_cpu_init(Object *obj) { }\n-static void hexagon_v73_cpu_init(Object *obj) { }\n-\n static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model)\n {\n ObjectClass *oc;\n@@ -377,11 +370,21 @@ static void hexagon_cpu_class_init(ObjectClass *c, const void *data)\n cc->tcg_ops = &hexagon_tcg_ops;\n }\n \n-#define DEFINE_CPU(type_name, initfn) \\\n- { \\\n- .name = type_name, \\\n- .parent = TYPE_HEXAGON_CPU, \\\n- .instance_init = initfn \\\n+static void hexagon_cpu_class_base_init(ObjectClass *c, const void *data)\n+{\n+ HexagonCPUClass *mcc = HEXAGON_CPU_CLASS(c);\n+ /* Make sure all CPU models define a HexagonCPUDef */\n+ g_assert(!object_class_is_abstract(c) && data != NULL);\n+ mcc->hex_def = data;\n+}\n+\n+#define DEFINE_CPU(type_name, version) \\\n+ { \\\n+ .name = type_name, \\\n+ .parent = TYPE_HEXAGON_CPU, \\\n+ .class_data = &(const HexagonCPUDef) { \\\n+ .hex_version = version, \\\n+ } \\\n }\n \n static const TypeInfo hexagon_cpu_type_infos[] = {\n@@ -394,13 +397,20 @@ static const TypeInfo hexagon_cpu_type_infos[] = {\n .abstract = true,\n .class_size = sizeof(HexagonCPUClass),\n .class_init = hexagon_cpu_class_init,\n+ .class_base_init = hexagon_cpu_class_base_init,\n },\n- DEFINE_CPU(TYPE_HEXAGON_CPU_V66, hexagon_v66_cpu_init),\n- DEFINE_CPU(TYPE_HEXAGON_CPU_V67, hexagon_v67_cpu_init),\n- DEFINE_CPU(TYPE_HEXAGON_CPU_V68, hexagon_v68_cpu_init),\n- DEFINE_CPU(TYPE_HEXAGON_CPU_V69, hexagon_v69_cpu_init),\n- DEFINE_CPU(TYPE_HEXAGON_CPU_V71, hexagon_v71_cpu_init),\n- DEFINE_CPU(TYPE_HEXAGON_CPU_V73, hexagon_v73_cpu_init),\n+ DEFINE_CPU(TYPE_HEXAGON_CPU_V5, HEX_VER_V5),\n+ DEFINE_CPU(TYPE_HEXAGON_CPU_V55, HEX_VER_V55),\n+ DEFINE_CPU(TYPE_HEXAGON_CPU_V60, HEX_VER_V60),\n+ DEFINE_CPU(TYPE_HEXAGON_CPU_V61, HEX_VER_V61),\n+ DEFINE_CPU(TYPE_HEXAGON_CPU_V62, HEX_VER_V62),\n+ DEFINE_CPU(TYPE_HEXAGON_CPU_V65, HEX_VER_V65),\n+ DEFINE_CPU(TYPE_HEXAGON_CPU_V66, HEX_VER_V66),\n+ DEFINE_CPU(TYPE_HEXAGON_CPU_V67, HEX_VER_V67),\n+ DEFINE_CPU(TYPE_HEXAGON_CPU_V68, HEX_VER_V68),\n+ DEFINE_CPU(TYPE_HEXAGON_CPU_V69, HEX_VER_V69),\n+ DEFINE_CPU(TYPE_HEXAGON_CPU_V71, HEX_VER_V71),\n+ DEFINE_CPU(TYPE_HEXAGON_CPU_V73, HEX_VER_V73),\n };\n \n DEFINE_TYPES(hexagon_cpu_type_infos)\n","prefixes":["v3","1/8"]}