{"id":2197353,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2197353/?format=json","project":{"id":21,"url":"http://patchwork.ozlabs.org/api/1.0/projects/21/?format=json","name":"Linux Tegra Development","link_name":"linux-tegra","list_id":"linux-tegra.vger.kernel.org","list_email":"linux-tegra@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260217173457.18628-7-akhilrajeev@nvidia.com>","date":"2026-02-17T17:34:55","name":"[6/8] dmaengine: tegra: Use iommu-map for stream ID","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"95eefd9d78a956bcb1d6e1c0ff0a6ac3c26c7a6c","submitter":{"id":81965,"url":"http://patchwork.ozlabs.org/api/1.0/people/81965/?format=json","name":"Akhil R","email":"akhilrajeev@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260217173457.18628-7-akhilrajeev@nvidia.com/mbox/","series":[{"id":492464,"url":"http://patchwork.ozlabs.org/api/1.0/series/492464/?format=json","date":"2026-02-17T17:34:49","name":"Add GPCDMA support in Tegra264","version":1,"mbox":"http://patchwork.ozlabs.org/series/492464/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2197353/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=Lq17AAYy;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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Register each channel separately for allowing it\nto use a separate IOMMU domain for the transfer.\n\nChannels will continue to use the same global stream ID if iommu-map\nproperty is not present in the device tree.\n\nSigned-off-by: Akhil R \n---\n drivers/dma/tegra186-gpc-dma.c | 62 +++++++++++++++++++++++++++-------\n 1 file changed, 49 insertions(+), 13 deletions(-)","diff":"diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c\nindex ce3b1dd52bb3..b8ca269fa3ba 100644\n--- a/drivers/dma/tegra186-gpc-dma.c\n+++ b/drivers/dma/tegra186-gpc-dma.c\n@@ -15,6 +15,7 @@\n #include \n #include \n #include \n+#include \n #include \n #include \n #include \n@@ -1403,9 +1404,12 @@ static int tegra_dma_program_sid(struct tegra_dma_channel *tdc, int stream_id)\n static int tegra_dma_probe(struct platform_device *pdev)\n {\n \tconst struct tegra_dma_chip_data *cdata = NULL;\n+\tstruct tegra_dma_channel *tdc;\n+\tstruct tegra_dma *tdma;\n+\tstruct dma_chan *chan;\n+\tbool use_iommu_map = false;\n \tunsigned int i;\n \tu32 stream_id;\n-\tstruct tegra_dma *tdma;\n \tint ret;\n \n \tcdata = of_device_get_match_data(&pdev->dev);\n@@ -1433,9 +1437,12 @@ static int tegra_dma_probe(struct platform_device *pdev)\n \n \ttdma->dma_dev.dev = &pdev->dev;\n \n-\tif (!tegra_dev_iommu_get_stream_id(&pdev->dev, &stream_id)) {\n-\t\tdev_err(&pdev->dev, \"Missing iommu stream-id\\n\");\n-\t\treturn -EINVAL;\n+\tuse_iommu_map = of_property_present(pdev->dev.of_node, \"iommu-map\");\n+\tif (!use_iommu_map) {\n+\t\tif (!tegra_dev_iommu_get_stream_id(&pdev->dev, &stream_id)) {\n+\t\t\tdev_err(&pdev->dev, \"Missing iommu stream-id\\n\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n \t}\n \n \tret = device_property_read_u32(&pdev->dev, \"dma-channel-mask\",\n@@ -1449,7 +1456,7 @@ static int tegra_dma_probe(struct platform_device *pdev)\n \n \tINIT_LIST_HEAD(&tdma->dma_dev.channels);\n \tfor (i = 0; i < cdata->nr_channels; i++) {\n-\t\tstruct tegra_dma_channel *tdc = &tdma->channels[i];\n+\t\ttdc = &tdma->channels[i];\n \n \t\t/* Check for channel mask */\n \t\tif (!(tdma->chan_mask & BIT(i)))\n@@ -1469,10 +1476,6 @@ static int tegra_dma_probe(struct platform_device *pdev)\n \n \t\tvchan_init(&tdc->vc, &tdma->dma_dev);\n \t\ttdc->vc.desc_free = tegra_dma_desc_free;\n-\n-\t\t/* program stream-id for this channel */\n-\t\ttegra_dma_program_sid(tdc, stream_id);\n-\t\ttdc->stream_id = stream_id;\n \t}\n \n \tret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(cdata->addr_bits));\n@@ -1517,20 +1520,53 @@ static int tegra_dma_probe(struct platform_device *pdev)\n \t\treturn ret;\n \t}\n \n+\tlist_for_each_entry(chan, &tdma->dma_dev.channels, device_node) {\n+\t\tstruct device *chdev = &chan->dev->device;\n+\n+\t\ttdc = to_tegra_dma_chan(chan);\n+\t\tif (use_iommu_map) {\n+\t\t\tchdev->coherent_dma_mask = pdev->dev.coherent_dma_mask;\n+\t\t\tchdev->dma_mask = &chdev->coherent_dma_mask;\n+\t\t\tchdev->bus = pdev->dev.bus;\n+\n+\t\t\tret = of_dma_configure_id(chdev, pdev->dev.of_node,\n+\t\t\t\t\t\t true, &tdc->id);\n+\t\t\tif (ret) {\n+\t\t\t\tdev_err(chdev, \"Failed to configure IOMMU for channel %d: %d\\n\",\n+\t\t\t\t\ttdc->id, ret);\n+\t\t\t\tgoto err_unregister;\n+\t\t\t}\n+\n+\t\t\tif (!tegra_dev_iommu_get_stream_id(chdev, &stream_id)) {\n+\t\t\t\tdev_err(chdev, \"Failed to get stream ID for channel %d\\n\",\n+\t\t\t\t\ttdc->id);\n+\t\t\t\tgoto err_unregister;\n+\t\t\t}\n+\n+\t\t\tchan->dev->chan_dma_dev = true;\n+\t\t}\n+\n+\t\t/* program stream-id for this channel */\n+\t\ttegra_dma_program_sid(tdc, stream_id);\n+\t\ttdc->stream_id = stream_id;\n+\t}\n+\n \tret = of_dma_controller_register(pdev->dev.of_node,\n \t\t\t\t\t tegra_dma_of_xlate, tdma);\n \tif (ret < 0) {\n \t\tdev_err_probe(&pdev->dev, ret,\n \t\t\t \"GPC DMA OF registration failed\\n\");\n-\n-\t\tdma_async_device_unregister(&tdma->dma_dev);\n-\t\treturn ret;\n+\t\tgoto err_unregister;\n \t}\n \n-\tdev_info(&pdev->dev, \"GPC DMA driver register %lu channels\\n\",\n+\tdev_info(&pdev->dev, \"GPC DMA driver registered %lu channels\\n\",\n \t\t hweight_long(tdma->chan_mask));\n \n \treturn 0;\n+\n+err_unregister:\n+\tdma_async_device_unregister(&tdma->dma_dev);\n+\treturn ret;\n }\n \n static void tegra_dma_remove(struct platform_device *pdev)\n","prefixes":["6/8"]}